SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022
Public

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4. SDI II IP Core Parameters

Note: For SDI II design example parameters, refer to the respective SDI II design example user guides.
Table 12.   SDI II IP Core Parameters
Note: Transceiver Options are available only for Arria V, Cyclone V, and Stratix V devices.

Parameter

Value

Description

Configuration Options

Video standard

SD-SDI, HD-SDI, 3G-SDI, HD-SDI dual link, Dual rate (up to HD-SDI), Triple rate (up to 3G-SDI), Multi rate (up to 12G-SDI), 12G-SDI

Sets the video standard.

  • SD-SDI—disables option for line insertion and extraction, and CRC generation and extraction
  • HD-SDI—enables option for in line insertion and extraction and CRC generation and extraction
  • Dual-, triple-, or multi-rate SDI—includes the processing blocks for the respective supported rates. Logics for bypass paths and to automatically switch between the input standards are included.
Note: SD-SDI, HD-SDI dual link, and Dual rate (up to HD-SDI) options are not available for Intel® Agilex™ F-tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices. Multi rate (up to 12G-SDI) option is not available for Arria V, Cyclone V, Stratix V, and Agilex devices . Triple rate (up to 3G-SDI) option is not available on Agilex devices in this release.
Note: Intel® Agilex™ F-tile device supports a 12G-SDI single rate as a preliminary feature. You must regenerate the IP when the Multi rate (up to 12G-SDI) feature is enabled.

SD interface bit width

10, 20

Selects the SD interface bit width. Only applicable for dual rate and triple rate.

Direction

Bidirectional, Receiver, Transmitter

Sets the port direction. The selection enables or disables the receiver and transmitter supporting logic appropriately.

  • Bidirectional—instantiates both the SDI transmitter and receiver.
  • Receiver—instantiates the SDI receiver
  • Transmitter—instantiates the SDI transmitter.
Transceiver and/or Protocol

Combined, Transceiver, Protocol

Selects the transceiver or protocol components, or both.

  • Transceiver—includes tx/rx_phy_mgmt/phy_adapter and Native PHY IP. This option is useful if you want to use the same transceiver component to support both SDI and ASI IP cores.
  • Protocol—allows each submodule to be removed or reused across different video standards. The transmitter and receiver data paths are independent from each other.
Note: This option is available only for Arria V, Cyclone V, and Stratix V devices.
Transceiver Options
Transceiver reference clock frequency

148.5/148.35 MHz,

74.25/74.175 MHz,

Selects the transceiver reference clock frequency.

The 74.25/74.175 MHz option is available only for HD-SDI and HD-SDI dual link video standards, and if you select CMU as the TX PLL.

Note: This option is not available if you select ATX PLL.
TX PLL type

CMU, ATX

Selects the transmitter PLL for TX or bidirectional ports.

ATX PLL is useful for bidirectional channels—you can use the ATX PLL as the transmitter PLL instead of the CMU PLL from another channel.

Note: This option is not available if you select ATX PLL.
Dynamic Tx clock switching

Off, Tx PLL switching, Tx PLL reference clock switching

  • Off: Disable dynamic switching
  • Tx PLL switching: Instantiates two PLLs, each with a reference input clock
  • Tx PLL reference clock switching: Instantiates a PLL with two reference input clocks.
Turn on this option to allow dynamic switching between 1 and 1/1.001 data rates.
Note: This option is only available for Arria V, Cyclone V, and Stratix V devices using TX or bidirectional ports, and all video standards except SD-SDI.

Receiver Options

Increase error tolerance level

On, Off

  • On: Error tolerance level = 15
  • Off: Error tolerance level = 4

Turn on this option to increase the tolerance level for consecutive missed end of active videos (EAVs), start of active videos (SAVs), or erroneous frames.

CRC error output

On, Off

  • On: CRC monitoring (Not applicable for SD-SDI mode)
  • Off: No CRC monitoring (saves logic)

Extract Payload ID (SMPTE ST 352)

On, Off

  • On: Extract payload ID
  • Off: No payload ID extraction (saves logic)

You must turn on this option for 3G-SDI, HD SDI dual link, triple-rate, and multi-rate modes. The extracted payload ID is required for consistent detection of the 1080p format.

It is compulsory to turn on this option for design example demonstration when you turn on Convert HD-SDI dual link to 3G-SDI (level B) or Convert 3G-SDI (level B) to HD-SDI dual link.

Rx core clock (rx_coreclk) frequency

100 MHz to 156.25 MHz,

148.5/148.35 MHz, 297.0/296.70 MHz
Selects the supported clock frequency for the rx_coreclk signal. This option is only available when you select Multi rate (up to 12G-SDI) in Receiver or Bidirectional mode. For other standards, the default frequency is 148.5/148.35 MHz.
Note: This option is only available for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices in the Intel® Quartus® Prime Pro Edition software.
Note: The frequency range - 100 MHz to 156.25 MHz is available in Intel® Agilex™ F-tile in the Intel® Quartus® Prime Pro Edition software.

Convert HD-SDI dual link to 3G-SDI (level B)

On, Off

  • On: Converts to level B (2 × SMPTE ST 292 HD-SDI mapping, including SMPTE ST 372 dual link mapping) for HD-SDI dual link receiver output.
  • Off: No conversion
Note: This option is only available for Arria V, Cyclone V, and Stratix V devices using HD-SDI dual link receiver.

Convert 3G-SDI (level B) to HD-SDI dual link

On, Off

  • On: Converts to HD-SDI dual link (direct image format mapping) for 3G-SDI receiver output.
  • Off: No conversion
Note: This option is only available for Arria V, Cyclone V, and Stratix V devices using 3G-SDI receiver.

Transmitter Options

Insert payload ID (SMPTE ST 352)

On, Off
  • On: Insert payload ID
  • Off: No payload ID insertion (saves logic)

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