5. SDI II IP Core Functional Description
The SDI II IP core implements a transmitter, receiver, or full-duplex interface.
The SDI II IP core consists of the following components:
- Protocol block—transmitter or receiver
- Transceiver blocks—PHY management & adapter and Native PHY IP
In the parameter editor, you can specify either protocol, transceiver, or combined blocks for your design. For example, if you have multiple protocol blocks in a design, you can multiplex them into one transceiver.
For the Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile devices, the SDI II IP core no longer provides the transceiver, and the TX PLL is no longer wrapped in the transceiver PHY. You must generate the transceiver and the TX PLL separately.
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