SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022
Public

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8.2.2.4. Reconfiguration Router Signals

Table below lists the signals for the reconfiguration router.

Table 33.  Reconfiguration Router Top Level SignalsThe listed signals are exported at the top level of the design example. Other signals—that are not exported—connect within the design example entity.
Note: These signals are available only when you use the Dynamic TX clock switching feature.

Refer to Dynamic TX Clock Switching for usage requirements.

Signal

Width

Direction

Description

ch1_<direction>_tx_start_reconfig

1

Input

Dynamic reconfiguration request signal for TX PLL dynamic switching at transmitter or duplex instance at channel 1.

ch1_<direction>_tx_pll_sel

1

Input

TX PLL select signal for TX PLL dynamic switching at transmitter or duplex instance at channel 1. This signal is also connected to xcvr_refclk_sel signal of the SDI instance.

ch1_<direction>_tx_reconfig_done

1

Output

Dynamic reconfiguration acknowledge signal for TX PLL dynamic switching at transmitter or duplex instance at channel 1.

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