SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.2.2.2. Transceiver Reconfiguration Controller Signals

Table 31.  Transceiver Reconfiguration Controller Signals for Arria V, Cyclone V, and Stratix V DevicesTable below lists the input signals for the transceiver reconfiguration controller. The listed signals are exported at the top level of the design example. Other signals—that are not exported—connects within the design example entity.
Signal Width Direction Description
reconfig_clk

1

Input

Clock signal for the transceiver reconfiguration controller and reconfiguration management/router. Refer to the transceiver reconfiguration controller section in the V-Series Transceiver PHY IP Core User Guide for information about the frequency range.

reconfig_rst

1

Input

Reset signal for the transceiver reconfiguration controller and reconfiguration management/router. This signal is active high and level sensitive.

Did you find the information on this page useful?

Characters remaining:

Feedback Message