SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022

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Document Table of Contents Reconfiguration Management Parameters

Tables below list the parameters for reconfiguration management.

Table 32.   Reconfiguration Management Parameters for Arria V, Cyclone V, and Stratix V Devices
Parameter Value Description
NUM_CHS 1 (minimum) Number of channels required to do reconfiguration.
  • Arria V
  • Arria V GZ
  • Cyclone V
  • Stratix V
Supported device family.
  • tx
  • rx
  • du
Direction of the core selected in the parameter editor. This parameter affects the logical channel number assigned in the generated example design.

If you are making any changes to the design, please ignore this parameter and assign the logical channel number correctly.

Refer to Expanding to Multiple Channels section to know how to assign the logical channel number.

  • tr
  • dl
Current video standard.

Specify dl for HD dual-link or tr for other standards.

  • 1
  • 2

The selected method to perform TX PLL reconfiguration for dynamic clock switching. Specify 1 to switch TX PLL or 2 to switch TX PLL reference clock.

The specified value must match the parameter value you select when you instantiate the IP core.

Refer to Dynamic TX Clock Switching section to know more about clock switching.