SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022
Public

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5.3.6. TX Sample

The TX sample submodule is a transmit oversampling block. It repeats each bit of the input word a given number of times and constructs the output words.

This submodule relies on the fact that the input data is only valid on 1/x of the clock cycles, where x is the oversampling factor. Both the input and output words are clocked from the same clock domain.

Table 14.  Oversampling Requirement The table below lists the number of times oversampling is required for the different video standards.
Real Video Rate vs. IP Mode SD-SDI HD-SDI Dual-Rate Triple-Rate Multi-Rate
SD-SDI 11 Not applicable 11 11 44
HD-SDI Not applicable 2 2 8
3G-SDI Not applicable Not applicable Not applicable Not applicable 4
6G-SDI Not applicable Not applicable Not applicable Not applicable 2
12G-SDI Not applicable Not applicable Not applicable Not applicable

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