SDI II Intel® FPGA IP User Guide

ID 683133
Date 2/16/2022
Public

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5.3.7. Clock Enable Generator

The clock enable generator is a simple logic that generates a clock enable signal.

The clock enable signal serves as a data valid signal, tx_datain_valid for the incoming video data signal, tx_datain. The video data signal is based on the incoming video standard signal, tx_std. The transmit parallel clock, tx_pclk, can be a single frequency of either 148.5 MHz or 148.35 MHz.

The clock enable generator generates a clock signal in the following conditions:

  • If the tx_datain signal is SD—generate a tx_datain_valid pulse every 5th and 11th clock cycle of the tx_pclk domain.
  • If the tx_datain signal is HD—generate a tx_datain_valid pulse every other clock cycle of the tx_pclk domain.
  • If the tx_datain signal is neither SD nor HD—the tx_datain_valid pulse remains high for 3G, 6G, or 12G.
Figure 21. Triple Rate Transmit Clocking Scheme

This figure illustrates the behavior of the tx_datain_valid pulse in each video standard.



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