Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

33.7.4. Example Calculation

This section demonstrates a calculation of the signal window for a Micron MT48LC4M32B2-7 SDRAM chip and design targeting the Stratix®  II EP2S60F672C5 device. This example uses a CAS latency (CL) of 3 cycles, and a clock frequency of 50 MHz. All SDRAM signals on the device are registered in I/O cells, enabled with the Fast Input Register and Fast Output Register logic options in the Intel® Quartus® Prime software.
Table 347.  Timing Parameters for Micron MT48LC4M32B2 SDRAM Device
Parameter Symbol Value (ns) in -7 Speed Grade
Min. Max.
Access time from CLK (pos. edge) CL = 3 tAC(3) 5.5
CL = 2 tAC(2) 8
CL = 1 tAC(1) 17
Address hold time tAH 1
Address setup time tAS 2
CLK high-level width tCH 2.75
CLK low-level width tCL 2.75
Clock cycle time CL = 3 tCK(3) 7
CL = 2 tCK(2) 10
CL = 1 tCK(1) 20
CKE hold time tCKH 1
CKE setup time tCKS 2
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 2
Data-in hold time tDH 1  
Data-in setup time tDS 2  
Data-out high-impedance time CL = 3 tHZ(3)   5.5
CL = 2 tHZ(2) 8
CL = 1 tHZ(1) 17
Data-out low-impedance time tLZ 1
Data-out hold time tOH 2.5  

The FPGA I/O Timing Parameters table below shows the relevant timing information, obtained from the Timing Analyzer section of the Intel® Quartus® Prime Compilation Report. The values in the table are the maximum or minimum values among all device pins related to the SDRAM. The variance in timing between the SDRAM pins on the device is small (less than 100 ps) because the registers for these signals are placed in the I/O cell.

Table 348.  FPGA I/O Timing Parameters
Parameter Symbol Value (ns)
Clock period tCLK 20
Minimum clock-to-output time tCO_MIN 2.399
Maximum clock-to-output time tCO_MAX 2.477
Maximum hold time after clock tH_MAX –5.607
Maximum setup time before clock tSU_MAX 5.936

You must compile the design in the Intel® Quartus® Prime software to obtain the I/O timing information for the design. Although Intel FPGA device family datasheets contain generic I/O timing information for each device, the Intel® Quartus® Prime Compilation Report provides the most precise timing information for your specific design.

The timing values found in the compilation report can change, depending on fitting, pin location, and other Intel® Quartus® Prime logic settings. When you recompile the design in the Intel® Quartus® Prime software, verify that the I/O timing has not changed significantly.

The following examples illustrate the calculations from figures Maximum SDRAM Clock Lag and Maximum Lead also using the values from the Timing Parameters and FPGA I/O Timing Parameters table.

The SDRAM clock can lag the controller clock by the lesser of Read Lag or Write Lag:

Read Lag = tOH(SDRAM) – tH_MAX(FPGA)

= 2.5 ns – (–5.607 ns) = 8.107 ns

or

Write Lag = tCLK – tCO_MAX(FPGA) – tDS(SDRAM)

= 20 ns – 2.477 ns – 2 ns = 15.523 ns

The SDRAM clock can lead the controller clock by the lesser of Read Lead or Write Lead:

Read Lead = tCO_MIN(FPGA) – tDH(SDRAM)

= 2.399 ns – 1.0 ns = 1.399 ns

or

Write Lead = tCLK – tHZ(3)(SDRAM) – tSU_MAX(FPGA)

= 20 ns – 5.5 ns – 5.936 ns = 8.564 ns

Therefore, for this example you can shift the phase of the SDRAM clock from –8.107 ns to 1.399 ns relative to the controller clock. Choosing a phase shift in the middle of this window results in the value (–8.107 + 1.399)/2 = –3.35 ns.