Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

10.4.2. ier_dlh

Identifier Title Offset Access Reset Value Description
ier_dlh Interrupt Enable and Divisor Latch High 0x4 RW 0x00000000

The ier_dlh (Interrupt Enable Register) may only be accessed when the DLAB bit [7] of the LCR Register is set to 0. Allows control of the Interrupt Enables for transmit and receive functions.This is a multi-function register. This register enables/disables receive and transmit interrupts and also controls the most-significant 8-bits of the baud rate divisor.

The Divisor Latch High Register is accessed when the DLAB bit (LCR[7] is set to 1). Bits[7:0] contain the high order 8-bits of the baud rate divisor. The output baud rate is equal to the system clock (clk) frequency divided by sixteen times the value of the baud rate divisor, as follows:

baud rate = (system clock freq) / (16 * divisor)

Note: With the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 system clock cycles should be allowed to pass before transmitting or receiving data.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- dlh7_4 edssi_dhl3 elsi_dhl2 etbei_dlh1 erbfi_dlh0
Table 76.  ier_dlh Fields
Bit Name/Identifier Description Access Reset
[31:8] - Reserved R 0x0
[7:4] DLH[7:4] (dlh7_4)
  • Divisor Latch High Register:

    Bit 4, 5, 6 and 7 of DLH value.

RW 0x0
[3] DLH[3] and Enable Modem Status Interrupt (edssi_dhl3)
  • Divisor Latch High Register:

    Bit 3 of DLH value.

  • Interrupt Enable Register:

    This is used to enable/disable the generation of Modem Status Interrupts. This is the fourth highest priority interrupt.

RW 0x0
[2] DLH[2] and Enable Receiver Line Status (elsi_dhl2)
  • Divisor Latch High Register:

    Bit 2 of DLH value.

  • Interrupt Enable Register:

    This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt

RW 0x0
[1] DLH[1] and Transmit Data Interrupt Control (etbei_dlh1)
  • Divisor Latch High Register:

    Bit 1 of DLH value.

  • Interrupt Enable Register:

    Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt.

RW 0x0
[0] DLH[0] and Receive Data Interrupt Enable (erbfi_dlh0)
  • Divisor Latch High Register:

    Bit 0 of DLH value.

  • Interrupt Enable Register:

    This is used to enable/disable the generation of the Receive Data Available Interrupt and the Character Timeout Interrupt (if FIFO's enabled). These are the second highest priority interrupts.

RW 0x0