Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

10.5. Intel FPGA 16550 Compatible UART Core Revision History

Document Version Intel® Quartus® Prime Version Changes
2021.10.18 21.3 Added Nios V processor in the description for Core Overview.
2021.03.29 21.1 Added support for Intel® eASIC™ N5X devices.
2019.07.16 19.1 Updated the description of stop bits in Line Control Register.
2018.05.07 18.0
  • Updated description of FIFO_DEPTH parameter.
  • Updated Figure: Hardware Auto Flow-Control Between two UARTs.
Date Version Changes
November 2017 2017.11.06 Removed the minimum clock requirement in the Table: Clock and Reset Signal Interface.
October 2016 2016.10.28 Two new registers: Updated:
  • lsr Bit [5]
  • fcr Bit [7:6]
  • New table added to iir section
December 2015 2015.12.16 Product ID changed in "16550 UART Release Information" section.
November 2015 2015.11.06 Updated the following topics:
June 2015 2015.06.12
  • Added "16550 UART General Programming Flow Chart" section
  • Added "16550 UART Release Information" section
  • Added "Address Map and Register Descriptions" section
  • Added Stick parity/Force parity feature into the "UART Features and Configurability" table in the "Feature Description" section
  • Updated "Interface" section with sout_oe signal details in the "Flow Control" table
  • Updated "Underrun" section
July 2014 2014.07.24 Initial Release.