Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

10.3.5.1. Public APIs

Table 66.  altera_16550_uart_open
Prototype: altera_16550_uart_state* altera_16550_uart_open (const char *name);
Include: <altera_16550_uart.h>
Parameters: name—the 16550 UART device name to open.
Returns: Pointer to 16550 UART or NULL if fail to open
Description Open 16550 UART device.
Table 67.  altera_16550_uart_close
Prototype: int altera_16550_uart_close(altera_16550_uart_state* sp, int flags);
Include: <altera_16550_uart.h>
Parameters: sp—the 16550 UART device name to close.

flags—for indicating blocking/non-blocking access for single/multi threaded.

Returns: None
Description: Closes 16550 UART device.
Table 68.  altera_16550_uart_read
Prototype: int altera_16550_uart_read(altera_16550_uart_state* sp, wchar_t* ptr, int len, int flags);
Include: <altera_16550_uart.h>
Parameters:

sp - The UART device

ptr – destination address

len – maximum length of the data

flags – for indicating blocking/non-blocking access for single/multi threaded

Returns: Number of bytes read
Description: Read data to the UART receiver buffer. UART required to be in a known settings prior executing this function
Table 69.  altera_16550_uart_write
Prototype: int altera_16550_uart_write(altera_16550_uart_state* sp, const wchar_t* ptr, int len, int flags);
Include: <altera_16550_uart.h>
Parameters:

sp - The UART device

ptr – source address

len – maximum length of the data

flags – for indicating blocking/non-blocking access for single/multi threaded

Returns: Number of bytes written
Description: Writes data to the UART transmitter buffer. UART required to be in a known settings prior executing this function
Table 70.  alt_16550_uart_config
Prototype: alt_u32 alt_16550_uart_config(altera_16550_uart_state* sp, UartConfig *setting);
Include: <altera_16550_uart.h>
Parameters:

sp - The UART device

setting – UART configuration structure to configure UART (refer to UART device structure)

Returns: Return 0 for success otherwise fail
Description: Configure UART per user input before initiating read or write