Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

15.8.1. Optional Status Retrieval API

Table 140.  alt_avalon_i2c_master_target_get
Prototype void alt_avalon_i2c_master_target_get (ALT_AVALON_I2C_DEV_t * i2c_dev, alt_u32 * target_addr)
Include <altera_avalon_i2c.h>
Parameters
  • i2c_dev - A pointer to the I2C controller device block instance.
  • target_addr - The 7 or 10 bit agent target address.
Returns -
Description This function returns the current target address.
Table 141.  alt_avalon_i2c_master_config_get
Prototype void alt_avalon_i2c_master_config_get (ALT_AVALON_I2C_DEV_t *i2c_dev, ALT_AVALON_I2C_MASTER_CONFIG_t* cfg)
Include <altera_avalon_i2c.h>
Parameters
  • i2c_dev - A pointer to the I2C controller device block instance.
  • cfg - Pointer to a ALT_AVALON_I2C_MASTER_CONFIG_t structure for holding the returned I2C host mode configuration parameters.
Returns -
Description Populates the host mode configuration structure (type ALT_AVALON_I2C_ADDR_MODE_t) from registers.
Table 142.  alt_avalon_i2c_master_config_speed_get
Prototype alt_avalon_i2c_master_config_speed_get (ALT_AVALON_I2C_DEV_t *i2c_dev, const ALT_AVALON_I2C_MASTER_CONFIG_t* cfg, alt_u32 * speed_in_hz)
Include <altera_avalon_i2c.h>
Parameters
  • i2c_dev - A pointer to the I2C controller device block instance.
  • cfg - Pointer to a ALT_AVALON_I2C_MASTER_CONFIG_t structure for holding the returned I2C host mode configuration parameters.
  • speed_in_hz - Speed (Hz) the I2C bus is currently configured at based on the cfg structure (not necessarily on the hardware settings). To get the hardware speed first populate the cfg structure with the alt_avalon_i2c_master_config_get() function.
Returns ALT_AVALON_I2C_SUCCESS - Indicates successful status. Otherwise, one of the ALT_AVALON_I2C_* status codes is returned. All failing return values are < 0.
Description This utility function returns the speed in hertz (Hz) based on the contents of the passed in configuration structure.
Table 143.  alt_avalon_i2c_int_status_get
Prototype void alt_avalon_i2c_int_status_get (ALT_AVALON_I2C_DEV_t *i2c_dev, alt_u32 *status)
Include <altera_avalon_i2c.h>
Parameters
  • i2c_dev - A pointer to the I2C controller device block instance.
  • status - A pointer to a bit mask of the active \ref ALT_AVALON_I2C_STATUS_t interrupt and status conditions.
Returns -
Description This function returns the current value of the I2C controller interrupt status register value which reflects the current I2C controller status conditions that are not disabled (or masked).
Table 144.  alt_avalon_i2c_int_raw_status_get
Prototype void alt_avalon_i2c_int_raw_status_get (ALT_AVALON_I2C_DEV_t *i2c_dev, alt_u32 *status)
Include <altera_avalon_i2c.h>
Parameters
  • i2c_dev - A pointer to the I2C controller device block instance.
  • status - A pointer to a bit mask of the active \ref ALT_AVALON_I2C_STATUS_t interrupt and status conditions.
Returns -
Description

This function returns the current value of the I2C controller raw interrupt status register value which reflects the current I2C controller status conditions regardless of whether they are disabled/masked or not.

Table 145.  alt_avalon_i2c_tfr_cmd_fifo_threshold_get
Prototype void alt_avalon_i2c_tfr_cmd_fifo_threshold_get (ALT_AVALON_I2C_DEV_t *i2c_dev, ALT_AVALON_I2C_TFR_CMD_FIFO_THRESHOLD_t *threshold)
Include <altera_avalon_i2c.h>
Parameters
  • i2c_dev - A pointer to the I2C controller device block instance.
  • threshold - The current threshold value.
Returns -
Description Gets the current Transfer Command FIFO threshold level value.
Table 146.  alt_avalon_i2c_rx_fifo_threshold_get
Prototype  
Include <altera_avalon_i2c.h>void alt_avalon_i2c_rx_fifo_threshold_get (ALT_AVALON_I2C_DEV_t *i2c_dev, ALT_AVALON_I2C_RX_DATA_FIFO_THRESHOLD_t *threshold)
Parameters
  • i2c_dev - A pointer to the I2C controller device block instance.
  • threshold - The current threshold value.
voidReturns -
Description Gets the current receive FIFO threshold level value.