Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

10.2.2. Interface

The Soft UART will have the following signal interface, exposed using _hw.tcl through Platform Designer software.

Table 55.  Clock and Reset Signal Interface
Pin Name Direction Description
clk Input

Avalon® clock sink

rst_n Input

Avalon® reset sink

Asynchronous assert, Synchronous deassert active low reset.

Interconnect fabric expected to perform synchronization – UART and interconnect is expected to be placed in the same reset domain to simplify system design

Table 56.   Avalon® -MM Agent
Pin Name Width Direction Description
addr 9 Input

Avalon® -MM Address bus

Highest addressable byte address is 0x118 so a 9-bit width is required

read   Input Avalon® -MM Read indication
readdata 32 Output Avalon® -MM Read Data Response from the agent
write   Input Avalon® -MM Write indication
writedata 32 Input Avalon® -MM Write Data
Table 57.  Interrupt Interface
Pin Name Direction Description
intr Output Interrupt signal
Table 58.  Flow Control
Pin Name Direction Description
sin Input Serial Input from external link.
sout Output Serial Output to external link.
sout_oe Output Output enable for Serial Output to external link.

sout_oe signal will be high when the UART is transmitting and low when the UART is IDLE.

Table 59.  Modem Control and Status
Pin Name Direction Description
cts_n Input Clear to Send
rts_n Output Request to Send
dsr_n Input Data Set Ready
dcd_n Input Data Carrier Detect
ri_n Input Ring Indicator
dtr_n Output Data Terminal Ready
out1_n Output User Designated Output1
out2_n Output User Designated Output2
Table 60.  DMA Sideband Signals
Pin Name Direction Description
dma_tx_ack_n Input TX DMA acknowledge
dma_rx_ack_n Input RX DMA acknowledge
dma_tx_req_n Output TX DMA request
dma_rx_req_n Output RX DMA request
dma_tx_single_n Output TX DMA single request
dma_rx_single_n Output RX DMA single request