Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

31.5.8. Component Configuration 1 Register

Bit Name Description
0 BURST_ENABLE Indicates burst transfer:
  • 0: Burst mode is disabled
  • 1: Burst mode is enabled
1 BURST_WRAPPING_SUPPORT Indicates burst wrapping support:
  • 0: Burst wrapping is disabled
  • 1: Burst wrapping is enabled
2 CHANNEL_ENABLE Indicates channel support in data streaming interface:
  • 0: Channel support is disabled
  • 1: Channel support is enabled
5:3 CHANNEL_WIDTH Indicates the number of channel used in data streaming interface. The number of channel is CHANNEL_WIDTH + 1:
  • 0: 1 channel
  • 1: 2 channels
  • 2: 3 channels
  • ...
  • 7: 8 channels
9:6 DATA_FIFO_DEPTH Indicates the depth of internal data path fifo. The depth of the data path fifo is 2(DATA_FIFO_DEPTH + 4):
  • 0: Depth of 16
  • 1: Depth of 32
  • 2: Depth of 64
  • ...
  • 8: Depth of 4096
  • 9 to 15 : Reserved
12:10 DATA_WIDTH Indicates the width of data path. The width of data path is 2(DATA_WIDTH + 3):
  • 0: Width of 8
  • 1: Width of 16
  • 2: Width of 32
  • ...
  • 7: Width of 1024
15:13 DESCRIPTOR_FIFO_DEPTH Indicates the depth of descriptor fifo. The depth of descriptor fifo is 2(DESCRIPTOR_FIFO_DEPTH + 3):
  • 0: Width of 8
  • 1: Width of 16
  • 2: Width of 32
  • ...
  • 7: Width of 1024
17:16 DMA_MODE Indicates the transfer mode:
  • 0: Memory-Mapped to Memory-Mapped
  • 1: Memory-Mapped to Streaming
  • 2: Streaming to Memory-Mapped
  • 3: Reserved
18 ENHANCED_FEATURES Indicates extended features support:
  • 0: Extended features is disabled
  • 1: Extended features is enabled
19 ERROR_ENABLE Indicates error support in data streaming interface:
  • 0: Error support is disabled
  • 1: Error support is enabled
22:20 ERROR_WIDTH Indicates the number of error lines in data streaming interface. The number of error lines is ERROR_WIDTH + 1:
  • 0: 1 error line
  • 1: 2 error lines
  • 2: 3 error lines
  • ...
  • 7: 8 error lines
26:23 MAX_BURST_COUNT Indicates the maximum burst count. The maximum burst count is 2(MAX_BURST_COUNT + 1):
  • 0: Burst count of 2
  • 1: Burst count of 4
  • 2: Burst count of 8
  • ...
  • 9: Burst count of 1024
  • 10 to 15 : Reserved
31:27 MAX_BYTE Indicates the maximum transfer length. The maximum transfer length is 2(MAX_BYTE + 10):
  • 0: Transfer length of 1024
  • 1: Transfer length of 2048
  • 2: Transfer length of 4096
  • ...
  • 21: Transfer length of 2147483648