Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

32.4. Parameters

Table 334.  Configurable Parameters
Parameter Legal Values Description
Transfer mode Memory To Memory
Memory To Stream
Stream To Memory Configuration to use. For more information about these configurations, see the Memory-to-Memory Configuration section.
Enable bursting on descriptor read host On/Off If this option is on, the descriptor processor block uses Avalon® -MM bursting when fetching descriptors and writing them back in memory. With 32-bit read and write ports, the descriptor processor block can fetch the 256-bit descriptor by performing 8-word burst as opposed to eight individual single-word transactions.
Allow unaligned transfers On/Off If this option is on, the core allows accesses to non-word-aligned addresses. This option doesn’t apply for burst transfers.

Unaligned transfers require extra logic that may negatively impact system performance.

Enable burst transfers On/Off Turning on this option enables burst reads and writes.
Read burstcount signal width 1–16 The width of the read burstcount signal. This value determines the maximum burst read size.
Write burstcount signal width 1–16 The width of the write burstcount signal. This value determines the maximum burst write size.
Data width 8, 16, 32, 64 The data width in bits for the Avalon® -MM read and write ports.
Source error width 0–7 The width of the error signal for the Avalon® -ST source port.
Sink error width 0 – 7 The width of the error signal for the Avalon® -ST sink port.
Data transfer FIFO depth 2, 4, 8, 16, 32, 64 The depth of the internal data FIFO in memory-to-memory configurations with burst transfers disabled.

The SG-DMA controller core should be given a higher priority (lower IRQ value) than most of the components in a system to ensure high throughput.