Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

23.4.3. Register Map

You do not need to access the interval timer core directly via its registers if using the standard features provided in the HAL system library for the Nios® II and Nios® V processors. In general, the register map is only useful to programmers writing a device driver.

The Intel-provided HAL device driver accesses the device registers directly. If you are writing a device driver, and the HAL driver is active for the same device, your driver will conflict and fail to operate correctly.

The table below shows the register map for the 32-bit timer. The interval timer core uses native address alignment. For example, to access the control register value, use offset 0x4.

Table 255.  Register Map—32-bit Timer
Offset Name R/W Description of Bits
15 ... 4 3 2 1 0
0 status RW (1) RUN TO
1 control RW (1) STOP START CONT ITO
2 periodl RW Timeout Period – 1 (bits [15:0])
3 periodh RW Timeout Period – 1 (bits [31:16])
4 snapl RW Counter Snapshot (bits [15:0])
5 snaph RW Counter Snapshot (bits [31:16])
Notes :
  1. Reserved. Read values are undefined. Write zero.

For more information about native address alignment, refer to the System Interconnect Fabric for Memory-Mapped Interfaces.

Table 256.  Register Map—64-bit Timer
Offset Name R/W Description of Bits
15 ... 4 3 2 1 0
0 status RW (1) RUN TO
1 control RW (1) STOP START CONT ITO
2 period_0 RW Timeout Period – 1 (bits [15:0])
3 period_1 RW Timeout Period – 1 (bits [31:16])
4 period_2 RW Timeout Period – 1 (bits [47:32])
5 period_3 RW Timeout Period – 1 (bits [63:48])
6 snap_0 RW Counter Snapshot (bits [15:0])
7 snap_1 RW Counter Snapshot (bits [31:16])
8 snap_2 RW Counter Snapshot (bits [47:32])
9 snap_3 RW Counter Snapshot (bits [63:48])
Notes :
  1. Reserved. Read values are undefined. Write zero.

status Register

The status register has two defined bits.    

Table 257.  status Register Bits
Bit Name R/W/C Description
0 TO R/WC The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a host peripheral. Write 0 or 1 to the status register to clear the TO bit.
1 RUN R The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by a write operation to the status register.

control Register

The control register has four defined bits.

Table 258.  control Register Bits
Bit Name R/W/C Description
0 ITO RW If the ITO bit is 1, the interval timer core generates an IRQ when the status register’s TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.
1 CONT RW The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.
2 START (1) W Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.
3 STOP (1) W Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect.

If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.

Notes :
  1. Writing 1 to both START and STOP bits simultaneously produces an undefined result.

period_n Registers

The period_n registers together store the timeout period value. The internal counter is loaded with the value stored in these registers whenever one of the following occurs:

  • A write operation to one of the period_n register
  • The internal counter reaches 0

    The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle.

    Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.

Note: A timeout period value of 0 is not a supported use case. Software configures timeout period values greater than 0.

snap_n Registers

A host peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.