Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

50.2. Interface Signals

Figure 145. Interface Signals
Signal Name Type Width (bit) Description
Clock and Reset
RefClk Input 1 A fixed frequency interface clock of 50 MHz. It is driven by PHY.
Rstn Input 1 Active low reset signal. EMAC provides this signal and it is connected to the MII to RMII Converter core and the PHY.
RMII: Core to RMII PHY Transmit Interface
rmii_tx_d[1:0] Output 2 Transmit data.
rmii_tx_en Output 1 Transmit enable.
RMII: PHY to RMII Receive Interface
rmii_crs_dv Input 1 Multiplexed Carrier Sense or Data Valid Signal (RMII 1.2).
rmii_rx_d[1:0] Input 2 Receive data.
rmii_rx_err Input 1 Receive error.
MII: RMII Core to MAC Transmit Interface
tx_clk Output 1
Transmit clock:
  • 25 MHz in 100 Mbps speed mode
  • 2.5 MHz in 10 Mbps speed mode
m_tx_en Input 1 Transmit data valid synchronized signal to transmit clock.
m_tx_d[3:0] Input 4 Transmit data.
m_tx_err Input 1 Transmit error.
MII: MAC to RMII Core Receive Interface
rx_clk Output 1 Receive clock.
m_rx_en Output 1 Receive data valid (extracted from CRS_DV).
m_rx_err Output 1 Receive error.
m_rx_crs Output 1 Ethernet carrier sense signal.
m_rx_col Output 1 Ethernet collision signal.
m_rx_d[3:0] Output 4 Receive data.
Core Speed Selection
ena_10 Input 1 Indication that the MAC is configured to 10 Mbps throughput.