Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2021
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Core 26. On-Chip Memory II (RAM or ROM) 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core

3.4. Register Description

The csr interface in the Avalon® -ST Single Clock FIFO core provides access to registers. The table below describes the registers.
Table 10.  Register Description for Avalon® -ST Single-Clock FIFO
32-Bit Word Offset Name Access Reset Description
0 fill_level R 0 24-bit FIFO fill level. Bits 24 to 31 are unused.
1 Reserved Reserved for future use.
2 almost_full_threshold RW FIFO depth–1 Set this register to a value that indicates the FIFO buffer is getting full.
3 almost_empty_threshold RW 0 Set this register to a value that indicates the FIFO buffer is getting empty.
4 cut_through_threshold RW 0 0—Enables store and forward mode.
>0—Enables cut-through mode and specifies the minimum of entries in the FIFO buffer before the valid signal on the Avalon® -ST source interface is asserted. Once the FIFO core starts sending the data to the downstream component, it continues to do so until the end of the packet.

This register applies only when the Use store and forward parameter is turned on.

5 drop_on_error RW 0 0—Disables drop-on error.
1—Enables drop-on error.

This register applies only when the Use packet and Use store and forward parameters are turned on.

The in_csr and out_csr interfaces in the Avalon® -ST Dual Clock FIFO core reports the FIFO fill level. The table below describes the fill level.

Table 11.  Register Description for Avalon® -ST Dual-Clock FIFO
32-Bit Word Offset Name Access Reset Value Description
0 fill_level R 0 24-bit FIFO fill level. Bits 24 to 31 are unused.