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Visible to Intel only — GUID: lro1403292046276
Ixiasoft
Visible to Intel only — GUID: lro1403292046276
Ixiasoft
53.2. Background
The existing implementation of the MSI target at Intel FPGA PCIe RootPort translates the MSI TLP received into a write transaction via PCIe Hard IP Avalon® -MM Host port (RP_Master). No interrupt output directed to the host processor to kick start the service routine for the MSI sender is needed.