LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Public
Document Table of Contents

1.4.1. Verilog HDL Prototype

You can locate the Verilog HDL prototype in the Verilog Design File (.v) altera_mf.v in the < Intel® Quartus® Prime installation directory> \eda\synthesis directory.