LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Document Table of Contents Effects of DPA PLL Calibration

There are two notable effects when DPA PLL calibration is enabled: effect on the timing of the logic clocked by the PLL, and effect related to the merging PLLs.

During PLL phase calibration, the I/O timing is pulled in by quarter of the voltage-controlled oscillator (VCO) period. All outputs of the PLL, including the slow clock, are affected. All HSIO TX data from interfaces, clocked by the affected PLL, clocks out quarter of the VCO period earlier. Likewise, all HSIO RX data clocks quarter cycle out of phase with the VCO but has less time to be sampled. For the slow clock that drives the core and the system, there is a loss of quarter of the VCO period on internal timing, across clock domain transfers in the core. The quarter period-pull greatly affects a design that has cross-clock transfer without using a FIFO, and the two clocks are not from the same PLL.

If DPA PLL calibration is enabled, PLLs, between receiver and transmitter instances or multiple receiver instances, do not merge even if the Share PLLs for receivers and transmitters setting is enabled. To force merging of such PLLs, use FORCE_MERGE_PLLS=ON setting in the Intel® Quartus® Prime Settings File (.qsf).

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