LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Document Table of Contents

1.5.1. Receiver Modes

The physical medium connecting the transmitter and receiver LVDS channels may introduce a skew between the serial data and the source-synchronous clock. The instantaneous skew between each LVDS channel and the clock also varies with the jitter on the data and clock signals as seen by the receiver.

The three receiver modes provide different options to overcome skew between the source-synchronous clock (non-DPA, DPA) /reference clock (soft-CDR) and the serial data.

The ALTLVDS_RX IP core supports the following receiver modes: