LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Public
Document Table of Contents
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1.5.1.3.1. Clock Forwarding

In soft-CDR mode, the ALTLVDS_RX IP core divides the DPA clock and the data by the deserialization factor. The newly divided clock signal, rx_divfwdclk,is then placed on the PCLK network, which carries the clock signal to the core. In supported devices, each LVDS channel can be in soft-CDR mode and can drive the core using the PCLK network. The clock forwarding feature is supported in Arria II GX, Arria II GZ, Arria V, Arria V GZ, HardCopy III, HardCopy IV, Stratix III, Stratix IV, and Stratix® V devices.

Note:

For more information about periphery clock networks for specific devices, refer to the Clock Networks and PLLs chapter in volume 1 of the respective device handbook.

When using soft-CDR mode, the rx_reset port must not be asserted after the DPA training is asserted because the DPA continuously chooses new phase taps from the PLL to track parts per million (ppm) differences between the reference clock and incoming data. The parallel clock rx_outclock, generated by the left and right PLL, is also forwarded to the FPGA fabric.

Note:
  • For ppm tolerance specifications between the source clock and received data, refer to the appropriate device data sheet or device handbook for each device.
  • For more information about receiver modes, refer to the High-Speed Differential I/O Interfaces chapter in the respective device handbook.

The Standard Mode and No Output Register Mode sections describe the implementation of soft -CDR mode in the ALTLVDS_RX block.