1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
188.8.131.52.2. Standard Mode
The following figure shows the implementation of soft-CDR mode in standard mode. In standard mode, the first two stages of core-capture registers are created automatically by the ALTLVDS_RX parameter editor. You must clock any additional user registers from the positive edge of the rx_divfwdclk clock; using the negative edge makes it harder to meet timing, and the duty cycle is not guaranteed.
Figure 1. ALTLVDS_RX Block in Standard Mode
Note: For LVDS RX channel operating in soft-CDR mode, Intel recommends you to use rx_divfwdclk (instead of any static clock) as the SignalTap capturing clock. Using static clock as the SignalTap capturing clock leads to bit error during the SignalTap sampling.
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