LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Document Table of Contents Standard Mode

The following figure shows the implementation of soft-CDR mode in standard mode. In standard mode, the first two stages of core-capture registers are created automatically by the ALTLVDS_RX parameter editor. You must clock any additional user registers from the positive edge of the rx_divfwdclk clock; using the negative edge makes it harder to meet timing, and the duty cycle is not guaranteed.

Figure 1.  ALTLVDS_RX Block in Standard Mode

Note: For LVDS RX channel operating in soft-CDR mode, Intel recommends you to use rx_divfwdclk (instead of any static clock) as the SignalTap capturing clock. Using static clock as the SignalTap capturing clock leads to bit error during the SignalTap sampling.

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