1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
|IP Core||Features||Supported devices|
|ALTLVDS_TX and ALTLVDS_RX||Parameterizable data channel widths||All Stratix® , Arria® , and Cyclone® series devices.|
|Parameterizable serializer/deserializer (SERDES) factors|
|Registered input and output ports|
|Support for external phase-locked loops (PLL)|
|PLLs sharing between transmitters and receivers|
|PLL control signals|
|ALTLVDS_RX Only||Dynamic phase alignment (DPA) mode support1||All Stratix® and Arria® series devices.|
|Soft clock data recovery (CDR) mode support2|
|DPA PLL calibration support1||All Stratix® series devices.|
Note: Intel recommends implementing the Bus LVDS (BLVDS) I/O with user logic, instead of the ALTLVDS_TX and ALTLVDS_RX IP cores.
1 DPA is available starting from Stratix GX onwards. The first generation Stratix device family does not support DPA.
2 CDR is not available in the first generation Stratix device family and the Stratix II device family. However, soft-CDR is available in all other Stratix series including Stratix GX and Stratix II GX..