LVDS SERDES Transmitter / Receiver IP Cores User Guide

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ID 683062
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide x
1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.1. Features x
1.1.1. Resource Utilization and Performance
1.2. Parameter Settings x
1.2.1. ALTLVDS_TX Parameter Settings 1.2.2. ALTLVDS_RX Parameter Settings 1.2.3. Command Line Interface Parameters
1.3. Ports x
1.3.1. ALTLVDS_TX Ports 1.3.2. ALTLVDS_RX Ports
1.4. Prototypes and Component Declarations x
1.4.1. Verilog HDL Prototype 1.4.2. VHDL Component Declaration 1.4.3. VHDL LIBRARY-USE Declaration
1.5. Functional Description x
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
1.5.1. Receiver Modes x
1.5.1.1. DPA Mode 1.5.1.2. Non-DPA Mode 1.5.1.3. Soft-CDR Mode
1.5.1.3. Soft-CDR Mode x
1.5.1.3.1. Clock Forwarding 1.5.1.3.2. Standard Mode 1.5.1.3.3. No Output Register Mode
1.5.2. DPA PLL Calibration x
1.5.2.1. DPA PLL Calibration in Stratix IV ES Devices 1.5.2.2. DPA PLL Calibration in Arria II and Stratix IV Devices and Later 1.5.2.3. Effects of DPA PLL Calibration
1.5.3. Initialization and Reset x
1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX 1.5.3.2. Resetting the DPA 1.5.3.3. Aligning the Word Boundaries 1.5.3.4. Recommended Initialization and Reset Flow
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints x
1.5.4.1. Dedicated SERDES 1.5.4.2. SERDES in LEs 1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew 1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI 1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File
1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew x
1.5.4.3.1. Obtaining the RSKM Report 1.5.4.3.2. Obtaining the TCCS Report
1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI x
1.5.4.4.1. Constraining the Input Clock Signal
1.5.6. ALTLVDS IP Core in External PLL Mode x
1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode 1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide

1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode

The parameter editor provides the Use External PLL option. This option allows you to control PLL settings to support different data rates, dynamic phase shift, and other settings. In external PLL mode, you must instantiate a PLL IP core to generate the various clock and load enable signals.
Note: For Stratix® IV, Arria® II, Cyclone® IV, and Intel® Cyclone® 10 LP devices, use the ALTPLL IP core. For Stratix® V, Arria® V, and Cyclone® V devices use the Altera PLL IP core.

If you enable the Use External PLL option, you require the following signals from the PLL IP core:

  • Serial clock input to the SERDES of the ALTLVDS transmitter and receiver.
  • Load enable to the SERDES of the ALTLVDS transmitter and receiver.
  • Parallel clock to clock the transmitter FPGA fabric logic.
  • Parallel clock for the receiver rx_syncclock port and receiver FPGA fabric logic.
  • Asynchronous PLL reset port of the ALTLVDS receiver.

Generate the serial clock output, load enable output, and the parallel clock output on ports c0, c1, and c2, along with the locked signal of the PLL IP core instance. You can choose any of the PLL output clock ports to generate the interface clocks.

Note: The high-speed clock generated from the PLL is for clocking the LVDS SERDES circuitry only. Do not use the high-speed clock to drive other logic because the allowed frequency to drive the core logic is restricted by the PLL FOUT specification.
Table 12.  Signal Interface Between PLL IP Core and ALTLVDS IP CoreThis table lists the signal interface between the output ports of the PLL IP core and the input ports of the ALTLVDS transmitter and receiver.
From the PLL To the ALTLVDS Transmitter To the ALTLVDS Receiver

Serial clock output (c0)

Note: The serial clock output (c0) can only drive tx_inclock on the ALTLVDS transmitter and rx_inclock on the ALTLVDS receiver. This clock cannot drive the core logic.
tx_inclock (serial clock input to the transmitter) rx_inclock (serial clock input)
Load enable output (c1) tx_enable (load enable to the transmitter) rx_enable (load enable for the deserializer)
Parallel clock output (c2) Parallel clock used inside the transmitter core logic in the FPGA fabric rx_syncclock (parallel clock input) and parallel clock used inside the receiver core logic in the FPGA fabric
~(locked) —

pll_areset (asynchronous PLL reset port)

Note: The pll_areset signal is available for the LVDS receiver in external PLL mode if you turn on the DPA. This signal does not exist for LVDS transmitter instantiation when the external PLL option is enabled.
The rx_syncclock port is not always required by the LVDS receiver in external PLL mode. If it is required, the Intel® Quartus® Prime software automatically generates the port. Even if rx_syncclock (c2) is not used in the LVDS receiver, you must still use it to clock the FPGA fabric. The Intel® Quartus® Prime compiler errors out if this port is not connected, as shown in the following figure.
Note: When generating the ALTPLL IP core for Arria II devices, select the Left/Right PLL PLL type to set up the PLL for LVDS.

The following figure shows the connection between the PLL IP core and the ALTLVDS IP core.

Figure 8. LVDS Interface with the PLL IP Core


Table 13.  Example Settings to Generate Three Output Clocks using PLL IP CoreThis table shows an example with the parameter values that you can set in the PLL IP core parameter editor to generate three output clocks.
Parameter/Clock Setting
Serial clock Frequency = 1000 MHz
Parallel clock Frequency = 100 MHz (serial clock divided by the serialization factor)
LVDS data rate 1 Gbps
Serialization factor 10
Input reference clock Frequency = 100 MHz
c0
  • Frequency = 1000 MHz (multiplication factor = 10 and division factor = 1)
  • Phase shift = –180° with respect to the voltage-controlled oscillator (VCO) clock
  • Duty cycle = 50%
c1
  • Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
  • Phase shift = (10 - 2) × 360/10 = 288° [(deserialization factor - 2)/deserialization factor] × 360°
  • Duty cycle = (100/10) = 10% (100 divided by the serialization factor)
c2
  • Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
  • Phase shift = (–180/10) = –18° (c0 phase shift divided by the serialization factor)
  • Duty cycle = 50%
Phase shift calculations using RSKM equation assume that the input clock and serial data are edge aligned. The following figure shows that by introducing a phase shift of –180° to sampling clock (c0) ensures that the input data is center-aligned with respect to the c0.
Note: The phase shift example used in this section assumes that the clock and data are edge-aligned at the FPGA pins. For other clock relationships, Intel recommends that you create the ALTLVDS_TX and ALTLVDS_RX IP cores initially without using the external PLL option. Set the phase shifts you require in the parameter editor and then note the phase shift and duty cycle settings for the three PLL output clocks in the Intel® Quartus® Prime software Compilation Report (Resource > Fitter > PLL Usage section). Once you have the correct phase shift and duty cycle settings for your parameterization, you can implement the external PLL mode in your design. In the parameter editor for the PLL IP core, enter the phase shift and duty cycle values for each output clock based on the values you previously noted from the PLL Usage report.
Figure 9. Phase Relationship for External PLL Interface Signals


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