18.104.22.168. Dedicated SERDES
The ALTLVDS_TX and ALTLVDS_RX IP cores implemented in a dedicated SERDES and using the DPA mode are characterized and guaranteed to function correctly within the LVDS system. Refer to the respective device handbook for details about whether dedicated SERDES and DPA are supported for the device family. The Intel® Quartus® Prime compiler automatically ensures the associated delay chain settings are set correctly for the data path at the LVDS transmitter/receiver that uses the source-synchronous compensation mode of PLL operation.
You can optionally add false path constraints to the asynchronous input and output ports to avoid unconstrained path warnings. For non-DPA mode, you can optionally constrain the synchronous input ports to improve the accuracy of the receiver skew margin analysis.
The TimeQuest Timing Analyzer automatically adds the required multicycle path, false path, and clock uncertainty constraints to analyze timing for the dedicated SERDES if you add derive_pll_clocks to your Synopsys Design Constraints (.sdc) file.