LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Document Table of Contents No Output Register Mode

The following figure shows the implementation of soft-CDR mode in no-output register mode. In this mode, you must create the capture registers by the user logic. To ensure even slack for both setup and hold, you must clock the first capture register stage by the falling edge of the rx_divfwdclk clock and clock the second stage of the registers by the rising edge of the rx_divwdclk clock. The register clocking method gives the equivalent implementation as the standard mode implementation.

Figure 2.  ALTLVDS_RX Block in No Output Register Mode