LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Document Table of Contents Resetting the DPA

When the data becomes corrupted, you must reset the DPA circuitry using the rx_reset port and rx_fifo_reset port.

Assert the rx_reset port to reset the entire DPA block. This requires the DPA to be trained before it is ready for data capture.

Note: Intel recommends using the option to automatically reset the bit serial FIFO when the rx_dpa_locked signal rises for the first time, if available for your device family; otherwise, toggle the rx_fifo_reset port after rx_dpa_locked is asserted. This option ensures the synchronization FIFO is set with the optimal timing to transfer data between the DPA and high-speed LVDS clock domains.

Assert the rx_fifo_reset port to reset only the synchronization FIFO. This allows you to continue system operation without having to re-train the DPA. Using this port can fix data corruption because it resets the FIFO; however, it does not reset the DPA circuit. In Stratix GX, Stratix II, Stratix II GX, HardCopy II, and Arria GX devices, the rx_dpa_locked port remains in its previous state; if it was deasserted, it remains deasserted and you are not be able to use it to know when the DPA is using the ideal phase tap for data capture.

When the DPA is locked, the ALTLVDS block is ready to capture data. The DPA finds the optimal sample location to capture each bit. The next step is to set up the word boundary using custom logic to control the rx_channel_data_align port on a channel-by-channel basis.

The word aligner or the bit-slip circuit can be reset using the rx_cda_reset port. This circuit can be reset anytime and is not dependent on the PLL or DPA circuit operation.