LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Document Table of Contents External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode

If you instantiate the ALTLVDS IP core in external PLL mode, Intel recommends that you set up the data rate and clocking with the PLL IP core.
Note: For Stratix® IV, Arria® II, Cyclone® IV, and Intel® Cyclone® 10 LP devices, use the ALTPLL IP core. For Stratix® V, Arria® V, and Cyclone® V devices use the Altera PLL IP core.
  • For Arria® V, Arria® V GZ, and Stratix® V devices with ALTLVDS_RX configured in non-DPA mode, the external PLL must be in LVDS compensation mode.
  • For Cyclone® V devices, LVDS interfaces placed on the all edges must be in LVDS compensation mode.

For more information about PLL compensation modes, refer to the PLL chapter of the relevant device handbook.