LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Document Table of Contents Recommended Initialization and Reset Flow

Intel recommends that you follow these steps to initialize and reset the ALTLVDS IP cores:

  1. During entry into user mode, or anytime in user mode operation when the interface requires a reset, assert the pll_areset and rx_reset ports.
  2. Deassert the pll_areset port and monitor the rx_locked port (rx_locked is the PLL lock indicator).
  3. Deassert the rx_reset port after the rx_locked port becomes asserted and stable.
  4. Apply the DPA training pattern and allow the DPA circuit to lock. (If a training pattern is not available, any data with transitions is required to allow the DPA to lock.) Refer to the respective device data sheet for DPA lock time specifications.
  5. Wait for the rx_dpa_locked port to assert.
  6. Beginning with Stratix III, HardCopy III, Arria II GX, and Arria II GZ devices, assert rx_fifo_reset for at least one parallel clock cycle, and then de-assert rx_fifo_reset.
  7. Assert the rx_cda_reset port for at least one parallel clock cycle, and then deassert the rx_cda_reset port.
  8. Begin word alignment by applying pulses as required to the rx_channel_data_align port.
  9. When the word boundaries are established on each channel, the interface is ready for operation.