LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Public
Document Table of Contents
Give Feedback

1.2.3. Command Line Interface Parameters

Expert users can choose to instantiate and parameterize the IP core through the command-line interface using the clear box generator command. This method requires you to have command-line scripting knowledge.

The following table lists the parameters for the ALTLVDS_TX IP core.

Table 6.   ALTLVDS_TX Parameters
Parameter Type Description
common_rx_tx_pll String

Specifies whether the compiler uses the same PLL for both the LVDS receiver and the LVDS transmitter, or multiple LVDS receivers, or multiple LVDS transmitters, or both. You can use common PLLs if the same input clock source, same deserialization factor, same pll_areset source, and same data rates are used. The values are ON and OFF. If omitted, the default value is ON.

Only available for Arria® GX, Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® GX, Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV, and Stratix® V devices.

coreclock_divide_by Integer

Specifies the core clock output frequency to either be core clock or core clock divided by 2. The value are 1 or 2.

This parameter is only available when using odd SERDES factors. When using a divide-by factor of 1, fewer device resources are used, but you may not be able to achieve timing at higher data rates.

Intel® recommends using a divide-by factor of two for higher data rates. This parameter is available for the Cyclone® series.

deserialization_factor Integer

Specifies the number of bits per channel.

The following is the device support and its values with normal mode:

  • Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ: 1 to 10
  • Arria® GX: 1, 2, 4, to 10
  • Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP: 1, 2, 4, to 10
  • HardCopy® II, HardCopy® III, and HardCopy® IV: 1, 2, 4, to 10
  • Stratix® and Stratix® GX: 1, 2, 4, 7, 8, to 10
  • Stratix® II and Stratix® II GX: 1, 2, 4, to 10
  • Stratix® III, Stratix® IV, and Stratix® V: 1 to 10

Arria® GX, Arria® II GX, Arria® II GZ, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® GX, Stratix® II, Stratix® II GX, Stratix® III, and Stratix® IV devices have the values of 1, 2, 4, to 10 with SERDES using logic cells.

enable_clk_latency String Specifies whether the PLLs use clock latency. The values are ON and OFF.
implement_in_les String

Specifies whether to implement SERDES circuitry in logic cells, which allows the circuitry to behave similarly to Stratix® LVDS circuitry. You must use the implement_in_les parameter for SERDES functions that require data rates that are lower than the dedicated circuitry. The values are ON and OFF. For Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, and Intel® Cyclone® 10 LP devices, the value is always ON.

Available for all devices except the MAX series.

The ALTLVDS_TX IP core starts its operation at the first rising edge of the fast clock, after the PLL has locked. This is intended for slow speeds and the bit alignment might be different from a dedicated SERDES implementation.

inclock_data_alignment String

Specifies the phase alignment of the tx_in[] and tx_inclock input ports in terms of the tx_inclock frequency. The clock phase alignment for the inclock_data_alignment parameter specifies the positive phase shift needed for the clock for alignment with the data.

The following are the parameter values and its values in degrees (°):

  • EDGE_ALIGNED: 0°
  • 45_DEGREES: 45°
  • 90_DEGREES: 90°
  • 135_DEGREES: 135°
  • CENTER_ALIGNED: 180°
  • 225_DEGREES: 225°
  • 270_DEGREES: 270°
  • 315_DEGREES: 315°

If omitted, the default value is EDGE_ALIGNED.

Available for Arria® GX, Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® GX, Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV, and Stratix® V devices.

inclock_period Integer Specifies the input clock either by frequency (MHz in the parameter editor) or period (ps in HDL code). This parameter is required when the external PLL option is not used.
number_of_channels Integer Specifies the number of LVDS channels.
outclock_alignment String

Specifies the alignment of tx_outclock with respect to the VCO of a fast PLL. The clock phase alignment for the outclock_alignment parameter is data leading.

This parameter is only used by the RTL simulation model and has no affect on how the Fitter sets the PLL parameters.

Values are:

  • EDGE_ALIGNED: 0°
  • 45_DEGREES: 45°
  • 90_DEGREES: 90°
  • 135_DEGREES: 135°
  • CENTER_ALIGNED:180°
  • 225_DEGREES: 225°
  • 270_DEGREES: 270°
  • 315_DEGREES: 315°

If omitted, the default value is EDGE_ALIGNED.

Available for all devices excluding the MAX series.

outclock_divide_by Integer

Specifies the period of the tx_outclock port as [INCLOCK_PERIOD * OUTCLOCK_DIVIDE_BY] and the frequency of the tx_outclock port as [INCLOCK_PERIOD/OUTCLOCK_DIVIDE_BY]. The default value for this parameter is the value of the deserialization_factor parameter.

Only available for Arria® GX, Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® GX, Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV, and Stratix® V devices.

For more information about the DESERIALIZATION_FACTOR and outclock_divide_by values, refer to Table 7.

outclock_duty_cycle Integer

Specifies the external clock timing constraints. A value of 50 is not supported in the outclock_duty_cycle parameter when the following is true:

  • DESERIALIZATION_FACTOR value is 5, 7, or 9.
  • OUTCLOCK_DIVIDE_BY value is equal to the value of DESERIALIZATION_FACTOR.
  • OUTCLOCK_MULTIPLY_BY value is 2.

This is always true for Cyclone® II, Cyclone® III, Cyclone® IV, and Intel® Cyclone® 10 LP devices, and true for Arria® V, Arria® V GZ, Stratix® II, Stratix® III, Stratix® IV, and Stratix® V devices when the implement_in_les parameter value is set to ON.

outclock_multiply_by Integer

Specifies the multiplication factor. The values are 1 and 2. If omitted, the default value is 1.

Only available for Cyclone® , Cyclone® II, Stratix® , Stratix® GX, and Stratix® II devices.

outclock_phase_shift Integer This parameter is used to set the phase shift parameters used by the PLL.

Specifies the phase shift of the output clock relative to the input clock. Phase shifts of 0.0, 0.25, 0.5, or 0.75 times the input period (0, 90, or 270°) are implemented precisely. The allowed range for the phase shift is between 0 ps and 1 input clock period. If the phase shift is outside this range, the compiler adjusts it to fall within this range. For other phase shifts, the compiler chooses the closest allowed value. If omitted, the default value is 0.

outclock_resource String

Specifies the clock resource type to use with the tx_coreclock port. The values are AUTO, REGIONAL CLOCK, and GLOBAL CLOCK. If omitted, the default value is AUTO.

Only available for Arria® GX, Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® GX, Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV, and Stratix® V devices.

output_data_rate Integer

Specifies the data rate out of the PLL. The multiplication value for the PLL is OUTPUT_DATA_RATE/INCLOCK_PERIOD.

Only available for Arria® GX, Arria® II GX, Arria® II GZ, Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® GX, Stratix® II, Stratix® II GX, Stratix® III, and Stratix® IV devices.

pll_bandwidth_type String

Specifies the loop filter bandwidth control setting on the PLL. The values are LOW, MEDIUM, and HIGH.

This parameter is only available for the Stratix® II device.

pll_self_reset_on_loss_lock String

The values are ON and OFF. If omitted, the default value is OFF. When this parameter is enabled, the PLL is reset when it loses lock.

This parameter is valid for Arria® V, Arria® V GZ, Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, Stratix® , Stratix® II GX, Stratix® III, and Stratix® IV devices when the implement_in_les parameter is set is ON.

registered_input String

Indicates whether the tx_in[] port is registered. The values are ON, OFF, TX_INCLOCK, and TX_CORECLOCK. If omitted, the default value is ON when using the tx_coreclock port to register the data in logic elements.

The TX_INCLOCK and TX_CORECLOCK values are available for Arria® GX, Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® GX, Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV, and Stratix® V devices.

If the registered_input parameter is set to OFF, you must pre-register the tx_in[] port in the logic feeding the transmitter.

use_external_pll String

Specifies whether the ALTLVDS_TX IP core generates a PLL or connect to a user-specified PLL.

Intel® recommends instantiating the external PLL with the parameter editor.

Only available for Arria® GX, Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® GX, Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV, and Stratix® V devices.

use_no_phase_shift String When set to OFF, a phase shift of 90° is added to the clock to center the clock in the data. Use this parameter when the implement_in_les parameter value is set to ON for Cyclone® II, Stratix® II, Stratix® III, and Stratix® IV devices. The values are ON and OFF. If omitted, default value is ON. Intel® recommends setting this parameter to OFF unless you have completed a phase adjustment.

The following table lists the DESERIALIZATION_FACTOR and outclock_divide_by values.

Table 7.  DESERIALIZATION_FACTOR and OUTCLOCK_DIVIDE_BY Values
Devices DESERIALIZATION_FACTOR Value OUTCLOCK_DIVIDE_BY Value
Arria® GX, Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV, and Stratix® V 4 2
4
5 5
6 2
6
7 7
8 2
4
8
9 9
10 2
10
Stratix® and Stratix® GX 4 2
4
7 7
8 2
4
8
10 2
10
Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Cyclone® V, and Intel® Cyclone® 10 LP 4 2
4
8
5 2
5
10
6 2
6
12
7 2
7
14
8 2
4
8
16
9 2
9
18
10 2
4
10
20

The following table lists the parameters for the ALTLVDS_RX IP core.

Table 8.   ALTLVDS_RX Parameters
Parameter Type Description
buffer_implementation String

Specifies where to implement the buffer. The values are MUX, RAM, and LES. A value of MUX implements a multiplexer instead of buffer implementation. A value of RAM implements a buffer in RAM blocks. A value of LES implements a buffer in logic elements. The RAM and LES values use more logic, but result in the correct word alignment. If omitted, the default value is RAM.

To use the buffer_implementation parameter, the implement_in_les parameter must be turned ON. You can also use the buffer_implementation parameter with deserialization factors of 5, 7, or 9 only.

common_rx_tx_pll String Specifies whether the compiler uses the same PLL for both the LVDS receiver and the LVDS transmitter, or multiple LVDS receivers or multiple LVDS transmitters, or both. You can use common PLLs if the same input clock source, same deserialization factor, same pll_areset source, and same data rates are used. Values are ON and OFF. If omitted, the default value is ON.
data_align_rollover Integer Specifies, in pulses, when the DPA circuitry restores the serial data latency to 0. You must enable the rx_dpa_locked port and the enable_dpa_mode parameter if this parameter is specified. The legal integer value ranges from 1 to 11. If omitted, the default value is 4.
deserialization_factor Integer

Specifies the number of bits per channel.

The values of this parameter for each supported device in normal mode are as follows:

  • Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ: 1 to 10.
  • Arria® GX: 1, 2, 4, to 10.
  • Cyclone® series: 1, 2, 4, to 10.
  • HardCopy® II, HardCopy® III, and HardCopy® IV: 1, 2, 4, to 10.
  • Stratix® and Stratix® GX: 1, 2, 4, 7, 8, to 10.
  • Stratix® II and Stratix® II GX: 1, 2, 4, to 10.
  • Stratix® III, Stratix® IV, and Stratix® V: 1, 2, 3, 4, to 10.

Arria® GX, Arria® II GX, Arria® II GZ, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® II, Stratix® II GX, Stratix® III, and Stratix® IV have the values of 1, 2, 4, to 10 with SERDES using logic cells.

The values of this parameter for each supported device in DPA mode are as follows:

  • Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ: 1 to 10.
  • Arria® GX: 1, 2, 4, to 10.
  • HardCopy® II, HardCopy® III, and HardCopy® IV: 1, 2, 4, to 10.
  • Stratix® GX: 8 and 10.
  • Stratix® II and Stratix® II GX: 1, 2, 4, to 10.
  • Stratix® III, Stratix® IV, and Stratix® V: 1 to 10.
dpa_initial_phase_value Integer Specifies the initial phase value. The values are 0 through 7. If the parameter value is set to OFF, the dpa_initial_phase_value parameter is set to 0.
enable_dpa_calibration String The values are ON and OFF. The default value is ON. Set this parameter to ON to phase shift the PLL outputs when the dpa_pll_cal_busy signal is high.
enable_dpa_align_to_rising_edge_only String Specifies that the DPA aligns to the rising edge of data only. Values are ON and OFF. If omitted, the default value is OFF. A value of OFF specifies that the DPA aligns to both the rising and falling edge of data.
enable_dpa_fifo String Indicates whether the DPA FIFO buffer is enabled for this channel.You must enable the rx_dpa_locked port and enable_dpa_mode parameter if this parameter is specified. The values are ON and OFF. If omitted, the default value is ON. This parameter is available for Stratix® GX devices in DPA mode only.
enable_dpa_initial_phase_selection String Specifies whether the dpa_initial_phase_value parameter is enabled. The values are ON and OFF. If omitted, the default value is OFF. When set to OFF, the dpa_initial_phase_value parameter value is set to 0.
enable_dpa_mode String Turns on DPA mode. The values are ON and OFF. If omitted, the default value is OFF.
enable_dpa_pll_calibration String The values are ON and OFF. The default value is OFF. Set this parameter to ON or OFF if you are instantiating the ALTLVDS_RX IP core in DPA mode with PLL calibration.
enable_soft_cdr_mode String Specifies whether the rx_divfwdclk port is used. When set to ON, the rx_divfwdclk port is driven by the DPA clock, and then it is divided down by the deserialization factor. When set to ON, the DPA FIFO is bypassed and rx_fifo_reset and reset_fifo_on_first_lock are ignored. The values are ON and OFF. If omitted, the default is OFF.
implement_in_les String Specifies whether to implement SERDES circuitry in logic cells, which allows the circuitry to behave similar to Stratix® LVDS circuitry. Use the implement_in_les parameter for SERDES functions that require data rates that are lower than the dedicated circuitry. Values are ON and OFF. Note that the receiver IP core starts capturing the LVDS stream at the first rising edge of the fast clock, after the PLL has locked. This is intended for slow speeds and the bit alignment may be different from a hard SERDES implementation.
inclock_data_alignment String

Specifies the phase alignment of the rx_in and rx_inclock input ports in terms of the rx_inclock frequency. The clock phase alignment for the inclock_data_alignment parameter specifies the positive phase shift needed for the clock for alignment with the data.

This parameter is only used by the RTL simulation model and has no affect on how the Fitter sets the PLL parameters.

The following are the parameter values and the corresponding phase shifts in degrees (°):

  • EDGE_ALIGNED: 0°
  • 45_DEGREES: 45°
  • 90_DEGREES: 90°
  • 135_DEGREES: 135°
  • CENTER_ALIGNED: 180°
  • 225_DEGREES: 225°
  • 270_DEGREES: 270°
  • 315_DEGREES: 315°

If omitted, the default value is EDGE_ALIGNED.

inclock_period Integer Specifies the period or frequency of the rx_inclock port. The default time unit is an integer in picoseconds (ps). In AHDL designs only, strings, such as 50.5 MHz, are acceptable.
inclock_phase_shift Integer This parameter is used to set the phase shift parameters used by the PLL. Specifies a phase shift in 15° increments.
input_data_rate Integer Specifies the data rate into the PLL. The multiplication value for the PLL is INPUT_DATA_RATE/INCLOCK_PERIOD.
lose_lock_on_one_change String Specifies when the DPA circuitry should lose lock. You must enable the rx_dpa_locked port and the enable_dpa_mode parameter if this parameter is specified. Values are ON and OFF. If omitted, the default value is ON.
number_of_channels Integer Specifies the number of LVDS channels.
outclock_resource String Specifies the clock resource type to use with the rx_outclock port. The values are AUTO, Regional Clock, and Global Clock. If omitted, the default value is AUTO.
pll_operation_mode String Specifies the source synchronous mode for Cyclone® II and Stratix® II device LE PLLs. The values are NORMAL and SOURCE_SYNCHRONOUS. If omitted, the default value is NORMAL.
pll_self_reset_on_loss_lock String The values are ON and OFF. If omitted, the default value is OFF. When this parameter is enabled, the PLL is reset when it loses lock. This parameter is valid for Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, Stratix® III, and Stratix® IV devices when the implement_in_les parameter is set to ON.
port_rx_channel_data_align String Edge-sensitive bit-slip control signal. Each rising edge on this signal causes the data re-alignment circuitry to shift the word boundary by one bit. The minimum pulse width requirement is one parallel clock cycle. There is no maximum pulse width requirement. Determines if the rx_channel_data_align port is used or unused. The values are PORT_USED, PORT_UNUSED, and PORT_CONNECTIVITY. When set to PORT_USED, the rx_channel_data_align port is used. When set to PORT_UNUSED, the rx_channel_data_align port is unused. When set to PORT_CONNECTIVITY, the Intel® Quartus® Prime software checks the connectivity of the rx_channel_data_align port to determine port usage. If omitted, the default value is PORT_CONNECTIVITY.
port_rx_data_align String Determines if the rx_align_data_reg port is used or unused. The values are PORT_USED, PORT_UNUSED, and PORT_CONNECTIVITY. When set to PORT_USED, the rx_align_data_reg port is used. When set to PORT_UNUSED, the rx_align_data_reg port is unused. When set to PORT_CONNECTIVITY, the Intel® Quartus® Prime software checks the connectivity of the rx_align_data_reg port to determine port usage. If omitted, the default value is PORT_CONNECTIVITY.
registered_data_align_input String Specifies whether the rx_align_data_reg port is registered. The values are ON and OFF. If omitted, the default is ON. Only available for Stratix® and Stratix® GX devices.
registered_output String Indicates whether the rx_out[] port should be registered. The values are ON and OFF. If omitted, the default is ON. If the registered_output parameter is set to OFF, you should pre-register the rx_out[] port in the logic feeding the receiver.
reset_fifo_at_first_lock String Specifies when the bit-serial FIFO resets. Normally, the bit-serial FIFO is reset when the DPA circuitry is locked or reset through the rx_reset port. The rx_dpa_locked port and the enable_dpa_mode parameter must be enabled if this parameter is specified. The values are ON and OFF. If omitted, the default value is ON. Only available for Arria® GX, Arria® II GX, Arria® II GZ, Stratix® II and Stratix® II GX devices.
rx_align_data_reg String Controls byte alignment circuitry. If omitted, the default value is RISING_EDGE. This port is available for Stratix® III devices only.
use_coreclock_input String Indicates whether the rx_coreclk port or the clock from PLL is used as the non-peripheral clock. You must connect the rx_coreclk port if you turn on this parameter. The values are ON and OFF. If omitted, the default value is OFF. This parameter is only available for Stratix® GX devices. This parameter is available in DPA mode only.
use_external_pll String Specifies whether the ALTVDS_RX IP core generates a PLL or connect to a user-specified PLL. Intel® recommends instantiating the external PLL with the parameter editor. Only available for Arria® GX, Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, Cyclone® , Cyclone® II, Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix® , Stratix® GX. Stratix® II, Stratix® II GX, Stratix® III, Stratix® IV, and Stratix® V devices. This option is not available when using deserialization factor of 1 and 2 in the Cyclone® series.
use_no_phase_shift String The values are ON and OFF. If omitted, default value is ON. Intel® recommends setting this parameter to OFF unless you have done a phase adjustment. When set to OFF, a phase shift of 90° is added to the clock to center the clock in the data. Use this parameter when the pll_operation_mode parameter value is set to SOURCE_SYNCHRONOUS for Cyclone® II and Stratix® II devices.