Intel® Agilex™ Variable Precision DSP Blocks User Guide

ID 683037
Date 11/17/2022

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4.2.1. Configurations for Input, Pipeline, and Output Registers

The configurations for the input, pipeline, and output registers are restricted due to the timing model in Intel® Agilex™ devices. Therefore these registers only support certain configurations.

You must enable all registers within the same register level but you can use different clock enables. However, when port accumulate is connected to constant VCC, the register settings for accumulate_clken, accum_pipeline_clken, accum_2nd_pipeline_clken, and accum_adder_clken should be disabled to avoid register clear signal interrupting the constant VCC.

The following registers should have the same clock enable settings:
  • Registers adder_input_clken and accum_adder_clken when operation_mode is set to FP32 multiplication with accumulation mode, sum of two FP16 multiplication with accumulation mode, or FP16 vector three mode.
  • Registers fp16_mult_input_clken and fp32_adder_a_clken when in all FP16 operation modes except FP16 vector three mode.