Intel® Agilex™ Variable Precision DSP Blocks User Guide

ID 683037
Date 11/17/2022
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3.2.3.3. Complex Multiplication

The Intel® Agilex™ devices support the floating-point arithmetic single precision complex multiplier using four Intel® Agilex™ variable-precision DSP blocks.

Figure 42. Sample of Complex Multiplication Equation

The imaginary part [(a × d) + (b × c)] is implemented in the first two variable-precision DSP blocks, while the real part [(a × c) - (b × d)] is implemented in the next two variable-precision DSP blocks.

Figure 43. Complex Multiplication with Imaginary Result Using FP32 Single-precision Floating-point Arithmetic
Figure 44. Complex Multiplication with Result Real Using FP32 Single-precision Floating-point Arithmetic
Figure 45. Complex Multiplication with Imaginary Result Using FP16 Half-precision Floating-point Arithmetic
Figure 46. Complex Multiplication with Result Real Using FP16 Half-precision Floating-point Arithmetic