Intel® Agilex™ Variable Precision DSP Blocks User Guide

ID 683037
Date 11/17/2022
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8.4. Signals

Table 101.   LPM_MULT Intel® FPGA IP Core Input Signals
Signal Name Required Description
dataa[] Yes Data input.

The size of the input signal depends on the Dataa width parameter value.

datab[] Yes Data input.

The size of the input signal depends on the Datab width parameter value.

clock No Clock input for pipelined usage.

For Latency values other than 1 (default), the clock signal must be enabled.

clken No Clock enable for pipelined usage. When the clken signal is asserted high, the adder/subtractor operation takes place. When the signal is low, no operation occurs. If omitted, the default value is 1.
aclr No Asynchronous clear signal used at any time to reset the pipeline to all 0s, asynchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value.
sclr No Synchronous clear signal used at any time to reset the pipeline to all 0s, synchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value.
Table 102.   LPM_MULT Intel® FPGA IP Output signals
signal Name Required Description
result[] Yes Data output.

The size of the output signals depends on the Result width parameter.