184.108.40.206. Mapping Systolic Mode User View to Variable Precision Block Architecture View
The following figure shows implementation of the systolic FIR filter (a) using the Intel® Agilex™ variable precision DSP blocks (d) by retiming the register and restructuring the adder. Register B can be retimed into systolic registers at the chainin, ay and ax input paths as shown in (b). The end result of the register retiming is shown in (c). The location of the adder is then restructured to sum both the multipliers output. The adder result is send to chainout adder to sum with the chainin value from the previous DSP block as shown in (d).