Intel® Agilex™ Variable Precision DSP Blocks User Guide

ID 683037
Date 11/17/2022
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12. Document Revision History for the Intel® Agilex™ Variable Precision DSP Blocks User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.11.17 21.2 Corrected legend 7 in the Location of Pipeline Register for FP32 Operation Modes figure from "fp32_mult_b_clken" to "mult_pipeline_clken".
2021.08.13 21.2
  • Added the DSP Block Cascade Limit in Intel® Agilex™ Devices topic.
  • Removed the statements about the number of DSP blocks you can cascade as systolic FIR structure in the following topics:
    • 18-bit Systolic FIR Mode
    • 27-Bit Systolic FIR Mode
  • In the 27-Bit Systolic FIR Mode topic, removed the "Systolic registers are not required in this mode" statement. The registers are not available in the 27-bit systolic FIR mode.
  • Fixed broken links and updated related information sections throughout the document.
2021.02.05 20.3 Clarified that bfloat16 is Brain Floating Point in the Features topic.
2020.09.28 20.3
  • Updated the supported registers for 18 × 19 systolic mode in the Supported Register Configurations per Operation Modes table.
  • Updated guidelines when using systolic register in fixed-point arithmetic in the Systolic Register for Fixed-point Arithmetic topic.
2020.04.26 20.1
  • Updated values for Which multiplier implementation should be used? parameter for the LPM_MULT IP core.
2020.04.13 20.1
  • Removed chainin output feature from footnote (5) in the Supported Register Configurations per Operation Modes table.
2019.09.30 19.3
  • Clarified that input and output registers for fixed-point arithmetic are not reset after power up and users need to clear the registers manually before starting an operation.
  • Updated equation for the following operation modes:
    • FP32 Multiplication with Accumulation
    • Sum of Two FP16 Multiplication with Accumulation
  • Updated the Supported Register Configurations per Operation Modes table in the Configurations for Input, Pipeline, and Output Registers topic for fixed-point arithmetic.
  • Added information for Native Fixed Point DSP Intel® Agilex™ FPGA IP version 19.1.1.
  • Added information for Native Floating Point DSP Intel® Agilex™ FPGA IP version 19.1.0
  • Added information for ALTMULT_COMPLEX Intel® FPGA IP version 19.1.0
  • Added information for LPM_DIVIDE Intel® FPGA IP version 19.1.
  • Added information for LPM_MULT Intel® FPGA IP version 19.1.0
  • Added information for Multiply Adder Intel® FPGA IP version 19.1.0
2019.04.02 19.1 Initial release.