Intel® Agilex™ Variable Precision DSP Blocks User Guide

ID 683037
Date 11/17/2022
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10.4.10. FP16 Vector Three Mode Signals

Figure 81. FP16 Vector Three Mode Signals


Table 139.   Data Input and Output Signals
Signal Name Type Width Default Description
fp32_adder_a[31:0] Input 32 Low Input data bus to the FP32 adder.
fp16_mult_top_a[15:0] Input 16 Low Input data bus to the top FP16 multiplier.
fp16_mult_top_b[15:0] Input 16 Low Input data bus to the top FP16 multiplier.
fp16_mult_bot_a[15:0] Input 16 Low Input data bus to the bottom FP16 multiplier.
fp16_mult_bot_b[16:0] Input 16 Low Input data bus to the bottom FP16 multiplier.
fp32_chainin[31:0] Input 32 Low

Connect these signals to the chainout signals from the preceding floating-point DSP IP core.

fp32_result[31:0] Output 32 Output data bus from IP core.
fp32_chainout[31:0] Output 32 Connect these signals to the chainin signals of the next floating-point DSP IP core.
Table 140.   Dynamic Control Signal
Signal Name Type Width Default Description
accumulate Input 1 Low Input signal to enable or disable the accumulator feature. You can change the value of this signal during run-time.
  • 1: Enable feedback the adder's output.
  • 0: Disable the feedback mechanism.
Table 141.  Clock, Enable, and Clear Signals
Signal Name Type Width Default Description
clk[0] Input 1 Input clock for all registers.
ena[2:0] Input 3 Clock enable signals for all registers.

These signals are active-High.

clr[1:0] Input 2 Low These signals can be asynchronous or synchronous clear input signals for all registers. You may select the type of clear input signal using Type of clear signal parameter.

These signals are active-High.

For more information about clock enable restrictions for input registers, refer to the related information.

Table 142.  Exception Flag Signals
Signal Name Type Width Default Description
fp16_mult_top_overflow/fp16_mult_bot_overflow Output 1

This signal indicates if the top/bottom fp16 multiplier result is a larger value compared to the maximum presentable value.

1: If the multiplier result is a larger value compared to the maximum representable value and the result is cast to infinity.

0: If the multiplier result is not larger than the maximum presentable value.

fp16_mult_top_underflow/fp16_mult_bot_underflow Output 1

This signal indicates if the top/bottom fp16 multiplier result is a smaller value compared to the minimum presentable value.

1: If the multiplier result is a smaller value compared to the minimum representable value and the result is flushed to zero.

0: If the multiplier result is a larger than the minimum representable value.

fp16_mult_top_inexact/fp16_mult_bot_inexact Output 1

This signal indicates if the top/bottom fp16 multiplier result is an exact representation.

1: If the multiplier result is:
  • a rounded value or
  • a smaller value compared to the minimum representable value or
  • a larger value compared to the maximum representable value.

0: If the multiplier result does not meet any of the criteria above.

fp16_mult_top_invalid/fp16_mult_bot_invalid Output 1

This signal indicates if the top/bottom fp16 multiplier operation is ill-defined and produces an invalid result.

1: If the multiplier result is invalid and cast to qNaN.

0: If the multiplier result is not an invalid number.

fp16_adder_overflow/fp32_adder_overflow Output 1

This signal indicates if the FP16/FP32 adder result is a larger value compared to the maximum representable value.

1: If the adder result is a larger value compared to the maximum presentable value and the result is cast to infinity.

0: If the multiplier result is not larger than the maximum presentable value.

fp16_adder_underflow/fp32_adder_underflow Output 1

This signal indicates if the FP16/FP32 adder result is a smaller value compared to the minimum presentable value.

1: If the multiplier result is a smaller value compared to the minimum representable value and the result is flushed to zero.

0: If the multiplier result is a larger than the minimum representable value.

fp16_adder_inexact/fp32_adder_inexact Output 1

This signal indicates if the FP16/FP32 adder result is an exact representation.

1: If the adder result is:
  • a rounded value
  • a smaller value compared to the minimum representable value or
  • a larger value compared to the maximum representable value.

0: If the multiplier result does not meet any of the criteria above.

fp16_adder_invalid/fp32_adder_invalid Output 1

This signal indicates if the FP16/FP32 adder operation is ill-defined and produces an invalid result.

1: If the multiplier result is invalid and cast to qNaN.

0: If the multiplier result is not an invalid number.