Quartus Prime Pro Edition Help version 17.0

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  • Welcome to the Software
    • Welcome to the Quartus® Prime Pro Edition Software
      • Quartus® Prime Pro Edition Highlights
      • New Features in this Release
      • Terminology
      • Using Help Effectively
        • Opening the Glossary
        • Opening the Messages List
        • Using the Search
  • Managing Projects
    • Viewing Project Information
      • General Page (Options Dialog Box)
        • Syncrhonize Connections Between Tools
      • Project Navigator Window
      • Compilation Dashboard
      • About the Project Navigator
        • Hierarchy Tab:
        • Files Tab:
        • Design Units Tab:
        • IP Components Tab:
    • General Settings
      • Libraries Page
      • Options Dialog Box
      • Colors Page (Options Dialog Box) (All Editors)
      • Fonts Page (Options Dialog Box) (All Editors)
      • General Page (Options Dialog Box)
      • License Setup Page (Options Dialog Box)
      • Processing Page (Options Dialog Box)
    • Project Settings
      • Settings Dialog Box
      • General Page (Settings Dialog Box)
        • Revision Type
      • Libraries Page (Settings Dialog Box)
      • Files Page (Settings Dialog Box)
      • Default Parameters Page (Settings Dialog Box)
      • Signal Tap Logic Analyzer Page (Settings Dialog Box)
      • Logic Analyzer Interface Page (Settings Dialog Box)
      • PowerPlay® Power Analyzer Settings Page (Settings Dialog Box)
    • Power Settings
      • Operating Settings and Conditions Page (Settings Dialog Box)
      • Voltage Page (Settings Dialog Box)
      • Temperature Page (Settings Dialog Box)
    • Software Connectivity
      • Internet Connectivity Page (Options Dialog Box)
    • Customize Flow Dialog Box
  • Starting the Quartus® Prime Software (quartus.exe) From the Command Line
  • Global Menu Items and Dialog Boxes
    • About Quartus® Prime Dialog Box
    • Add Node to Signal Tap Logic Analyzer Command (Shortcut Menu)
    • Customize Dialog Box
    • Export Dialog Box (All Editors)
    • Find/Replace Dialog Boxes (All Other Editors)
      • Find what
    • Recent Commands (File Menu)
    • New Dialog Box
    • Nios® II Software Build Tools for Eclipse
    • Open Dialog Box
    • Page Setup Dialog Box
    • Print Dialog Box
    • Zoom Dialog Box
    • Customize Toolbar Dialog Box
    • Quartus® Prime Incompatible Project Dialog Box
    • Options Dialog Box
    • Print Topics Dialog Box
    • Select Family Dialog Box
    • quartus2.ini File
    • Tooltip Settings Page (Options Dialog Box)
    • About the Tasks Window
    • Add Current File to Project Command (Project Menu)
    • Create New LogicLock® Plus Region Command (Shortcut Menu)
    • Design Unit Properties Dialog Box (Shortcut Menu)
    • File Properties Dialog Box (Shortcut Menu)
    • Open in Main Window Command (Shortcut Menu)
    • Edit in Parameter Editor Command (Shortcut Menu)
    • Upgrade IP Components Dialog Box (Project Menu)
    • Remove File from Project Command (Shortcut Menu)
    • Save Project Command (File Menu)
    • Edit Flow Dialog Box
    • Tcl Scripts Dialog Box (Tasks Window)
    • Use Existing Project Settings Dialog Box
      • Use settings from last opened project
    • Create Aggregate Revision Dialog Box
    • Create Reconfigurable Revision Dialog Box
    • Copy Full Path Command (Right-Click Menu)
    • Copy File Name Command (Right-Click Menu)
  • About Simulating Designs
  • Running Timing Analysis
    • New SDC File Command (TimeQuest Timing Analyzer)
    • Open SDC File Command (TimeQuest Timing Analyzer)
    • Read SDC File Command
    • Set Operating Conditions Dialog Box (set_operating_conditions)
    • Report Timing Dialog Box
    • Report Minimum Pulse Width Dialog Box
    • Report False Path Dialog Box
    • Report Path Dialog Box
    • Report Exceptions Dialog Box
    • Report Bottlenecks Dialog Box
    • Report Net Timing Dialog Box
    • Report Skew Dialog Box (report_skew)
    • Report Max Skew Dialog Box (report_max_skew)
    • Report Net Delay
    • Report Metastability Command
    • Report Recovery Summary Command
    • Report Removal Summary Command
    • Report Timing Closure Recommendations Dialog Box
    • Report CDC Viewer Command
      • Report Custom CDC Viewer Command
  • Timing Analysis Settings
    • Set Clock Groups Dialog Box (set_clock_groups)
    • Set Clock Latency Dialog Box (set_clock_latency)
    • Set Clock Uncertainty Dialog Box (set_clock_uncertainty)
    • Set False Path Dialog Box (set_false_path)
    • Set Input Delay Dialog Box (set_input_delay)
    • Set Output Delay Dialog Box (set_output_delay)
    • Set Maximum Delay Dialog Box (set_max_delay)
    • Set Minimum Delay Dialog Box (set_min_delay)
    • Set Multicycle Path Dialog Box (set_multicycle_path)
  • Integrating Other EDA Tools
    • About Using EDA Simulators
  • Simulation Settings
    • About Integrating Other EDA Tools
    • Preparing for EDA Simulation
    • Running EDA Simulators
  • Simulation Tools
    • Active-HDL
      • Performing a Simulation of a Verilog HDL Design with the Active-HDL Software
      • Performing a Simulation of a VHDL Design with the Active-HDL Software
    • ModelSim
      • Setting Up a Project with the ModelSim Software
      • Performing a Timing Simulation with the ModelSim Software
    • ModelSim-Altera
      • Setting Up a Project with the ModelSim-Intel FPGA Edition Software
      • Performing a Functional Simulation with the ModelSim-Intel FPGA Edition Software
      • Performing a Timing Simulation with the ModelSim-Intel FPGA Edition Software
    • Incisive Enterprise Simulator
      • Performing a Functional Simulation with the Incisive Enterprise Simulator Software
      • Performing a Timing Simulation with the Incisive Enterprise Simulator Software
    • QuestaSim
      • Setting Up a Project with the QuestaSim Software
      • Compiling Libraries and Design Files with the QuestaSim Software
      • Performing a Functional Simulation with the QuestaSim Software
      • Performing a Timing Simulation with the QuestaSim Software
    • Riviera-PRO
      • Performing a Functional Simulation with the Riviera-PRO Software
      • Performing a Post-Synthesis Simulation with the Riviera-PRO Software
      • Performing a Gate-Level Simulation with the Riviera-PRO Software
    • VCS MX
      • Performing a Functional Simulation with the VCS MX Software
      • Performing a Timing Simulation with the VCS MX (VHDL) Software
    • VCS
      • Performing a Functional Simulation with the VCS Software
      • Performing a Timing Simulation with the VCS Software
  • Design Entry/Synthesis Tools
    • Precision RTL Synthesis Software
      • About Using the Precision RTL Synthesis Software with the Quartus® Prime Software
      • Setting Up the Precision RTL Synthesis Working Environment
      • Creating a Design for Use with the Precision RTL Synthesis Software
      • Setting Up a Project with the Precision RTL Synthesis Software
      • Assigning Design Constraints with the Precision RTL Synthesis Software
      • Generating EDIF Netlist Files with the Precision RTL Synthesis Software
    • Synplify Software
      • Setting Up the Synplify Working Environment
      • Creating a Design for Use with the Synplify Software
    • Setting Up the DK Design Suite Working Environment
  • Generating Output Files for Board-Level Tools
    • Generating Board-Level Timing Analysis Files
      • Setting Up the Tau Working Environment
      • Creating Stamp Model Files with the Quartus® Prime Software
      • Performing Timing Verification with the Tau Software
    • Generating Board-Level Symbol Output Files
      • Generating FPGA Xchange-Format Files for Use with Other EDA Tools
      • Generating PartMiner edaXML-Format Files for Use with Other EDA Tools
    • Generating Board-Level Signal Integrity Analysis Files
      • Generating HSPICE Simulation Deck Files for External Signal Integrity Analysis
    • Generating Boundary-Scan Description Language Files
      • Create Board-Level Boundary-Scan File Window (File Menu)
      • Generating Boundary-Scan Description Language Output Files with the Quartus® Prime Software
  • Synopsys® -Provided Logic Libraries
  • Example of Performing a Timing Simulation of a Synplify Verilog HDL Design with a Custom Megafunction Variation with the ModelSim Software
  • Using Project Revisions
    • Revisions Dialog Box
    • Compare Revisions Dialog Box
    • Create Revision Dialog Box
  • Archiving Projects
    • Advanced Archive Settings Dialog Box
    • Archive Project Dialog Box
  • Managing Project Databases
  • Creating Designs
    • Using the Block Editor
      • Block Diagram/Schematic File (New Dialog Box)
      • Block Properties Dialog Box (Shortcut Menu)
      • Block Symbol File (New Dialog Box)
      • Bus Properties Dialog Box
      • Conduit Properties Dialog Box
      • Create Design File from Selected Block Dialog Box
      • Create HDL Design File for Current File Dialog Box
      • Edit Selected Symbol Command (Shortcut Menu)
    • Using the Memory Editor
      • Go To Dialog Box
      • New Memory Initialization File Command ( Quartus® Prime Menu)
      • Open Memory Dialog Box
      • Show Delimiter Spaces Command (View Menu)
    • Using the Text Editor
      • Autocomplete Text Command (Edit Menu)
      • Insert Constraint Command (Shortcut Menu)
      • Insert File Command (Edit Menu)
      • Insert Template Dialog Box
      • Open AHDL Include File Command (Shortcut Menu)
      • Preferred Text Editor (Options Dialog Box)
      • Text Editor Page (Options Dialog Box)
  • Using HDL with the Quartus® Prime Software
    • Quartus® Prime Primitives
      • Primitives
      • List of Primitives
        • ALT_BIDIR_BUF Primitive
        • ALT_INBUF Primitive
        • ALT_INBUF_DIFF Primitive
        • ALT_IOBUF Primitive
        • ALT_OUTBUF Primitive
        • ALT_OUTBUF_DIFF Primitive
        • ALT_OUTBUF_TRI Primitive
        • AND Primitive
        • BAND (Block Design Files only) Primitive
        • BIDIR or INOUT Primitive/Port
        • BNAND (Block Design Files only) Primitive
        • BNOR (Block Design Files only) Primitive
        • BOR (Block Design Files only) Primitive
        • CARRY_SUM Primitive
        • CASCADE Primitive
        • CONSTANT Primitive
        • DFF Primitive
        • DFFE Primitive
        • DLATCH Primitive
        • EXP Primitive
        • GLOBAL Primitive
        • GND (Block Design Files only) Primitive
        • INPUT or IN Primitive/Port
        • JKFF Primitive
        • JKFFE Primitive
        • LATCH Primitive
        • LCELL Primitive
        • LUT_INPUT Primitive
        • LUT_OUTPUT Primitive
        • NAND Primitive
        • NOR Primitive
        • NOT Primitive
        • OPNDRN Primitive
        • OR Primitive
        • PARAM Primitive
        • Primitive/Port Interconnections
        • SOFT Primitive
        • SRFF Primitive
        • SRFFE Primitive
        • TFF Primitive
        • TFFE Primitive
        • Title Block Primitive
        • TRI Primitive
        • Unused Inputs to Primitives, Megafunctions & Macrofunctions
        • VCC (Block Design Files only) Primitive
        • WIRE (Block Design Files only) Primitive
        • XNOR Primitive
        • XOR Primitive
        • Pinstub Names in Primitives
        • WYSIWYG Atom Names Unavailable for Use as Primitive Instance Names
    • Managing IP in Quartus® Prime
      • About the IP Catalog and Parameter Editor
      • Upgrade IP Components Dialog Box
      • Megafunctions/LPM
  • HDL Language Support
  • Working with Qsys Pro
    • Qsys Pro Component Editor
      • Add Commands (Templates Menu) (Component Editor)
      • Qsys Pro Component Editor
      • Template Command (Qsys Pro Component Editor)
      • Files Tab (Qsys Pro Component Editor)
      • Parameters Tab (Qsys Pro Component Editor)
      • Interfaces Tab (Qsys Pro Component Editor)
    • Working with Presets in Qsys Pro
      • New Preset Dialog Box (Qsys Pro)
      • Presets Tab (Qsys Pro)
      • Update Preset Dialog Box (Qsys Pro)
    • Create a Qsys Pro System
      • Add Commands (Templates Menu) (Component Editor)
      • Custom Layouts (View Menu) (Qsys Pro)
      • Interconnect Requirements Tab (View Menu) (Qsys Pro)
      • Messages Tab (View Menu) (Qsys Pro)
      • New Component Command (File Menu) (Qsys Pro)
      • New System Command (File Menu) (Qsys Pro)
      • Add Instance Dialog Box (Qsys Pro)
      • Create Snythesis File From Signals Dialog Box (Qsys Pro)
      • IP Catalog (View Menu) (Qsys Pro)
    • Qsys Pro Commands
      • Assign Custom Instruction Opcodes Command (System Menu) (Qsys Pro)
      • Assign Base Addresses Command (System Menu) (Qsys Pro)
      • Assign Interrupt Numbers (System Menu) (Qsys Pro)
      • Browse Project Directory (File Menu) (Qsys Pro)
      • Archive System (File Menu)
      • Restore Archived System (File Menu)
      • Export System as qsys script (.tcl) (File menu)
      • Synchronize IP File References (File Menu)
      • Create Global Reset Network Command (System Menu) (Qsys Pro)
      • Generate Example Design (Generate Menu) (Qsys Pro)
      • Lock/Unlock Base Address Commands (Edit Menu) (Qsys Pro)
      • Nios® II Software Build Tools for Eclipse Command (Tools Menu) (Qsys Pro)
      • Nios® II Command Shell [gcc4] Command (Tools Menu) (Qsys Pro)
      • IP Search Path Options (Tools Menu)
      • Parameters Tab (View Menu) (Qsys Pro)
      • Recent Projects (File Menu) (Qsys Pro)
      • Refresh System Command (File Menu) (Qsys Pro)
      • Remove Dangling Connections Command (System Menu) (Qsys Pro)
      • Reset to IP Layout (View Menu) (Qsys Pro)
      • Reset to System Layout (View Menu) (Qsys Pro)
      • Show System With Qsys Pro Interconnect Command (System Menu) (Qsys Pro)
      • Options Dialog Box (Tools Menu) (Qsys Pro)
    • View a Qsys Pro System
      • Assignments Tab (View Menu) (Qsys Pro)
      • Block Symbol Tab (View Menu) (Qsys Pro)
      • Connections Tab (View Menu) (Qsys Pro)
      • Custom Layouts (View Menu) (Qsys Pro)
      • Element Docs Tab (Qsys Pro)
      • Hierarchy Tab (View Menu) (Qsys Pro)
      • Device Family Tab (View Menu) (Qsys Pro)
      • Parameters Tab (View Menu) (Qsys Pro)
      • Reset Domains (View Menu) (Qsys Pro)
      • Schematic Tab (View Menu) (Qsys Pro)
      • Set Color (Edit Menu) (Qsys Pro)
      • Clock Domains (View Menu) Qsys Pro)
      • Avalon Memory Mapped Domains (View Menu) (Qsys Pro)
      • Create Snythesis File From Signals Dialog Box (Qsys Pro)
      • Address Map Tab (View Menu) (Qsys Pro)
      • System Contents Tab (View Menu) (Qsys Pro)
      • Component Instantiation Editor (Component Instantiation Tab)
      • Interface Requirements Tab
      • System Info Tab
      • System Scripting (View Menu) (Qsys Pro)
      • Validate Component Footprint
      • Validate System Integrity
    • Generate in Qsys Pro
      • Generate Example Design (Generate Menu) (Qsys Pro)
      • Generate Testbench System (Generate Menu) (Qsys Pro)
      • Generate HDL (Generate Menu) (Qsys Pro)
      • Generate Example Design (Generate Menu) (Qsys Pro)
    • Debug in Qsys Pro
      • Instrumentation Tab (View Menu) (Qsys Pro)
  • BluePrint Planning
    • BluePrint Flow Control
    • BluePrint Assignments Tab
    • BluePrint Home Tab
    • BluePrint Plan Tab
    • BluePrint Reports Tab
    • Constraining Designs
      • Assign Groups
        • Group Dialog Boxes
    • Back-Annotate Pins
      • Back-Annotate Command (Shortcut Menu) (Pin Planner)
    • Manage I/O Pins
      • Pin Planner Command (Assignments Menu)
    • Set Up Top-Level Design File Window (Edit Menu)
    • Import Assignments
      • Import Assignments Dialog Box (Assignments Menu)
    • Edit Assignments
      • Assignment Editor Command (Assignments Menu)
  • Using Advisors for Design Optimization
    • About Advisors in the Quartus® Prime Software
    • Arria® 10 to Stratix® 10 Migration Advisor Command (Tools Menu)
    • Compilation Time Advisor Command (Tools Menu)
    • Power Optimization Advisor Command (Tools Menu)
    • Timing Optimization Advisor Command (Tools Menu)
  • Viewing Reports
    • Compilation Reports
      • Synthesis Reports
        • Synthesis Summary Reports
        • Synthesis Settings Reports
        • Parallel Compilation Report
        • Synthesis Source Files Read Report
        • Source Assignments Report
        • Parameter Settings by Entity Instance Report
        • Synthesis Optimization Results Reports
        • Synthesis Partition Reports
        • Synthesis Connectivity Checks Report
        • Synthesis Resources Reports
        • State Machines Report
      • Fitter Stage Reports
        • Fitter Resources Reports
        • Fitter I/O Rules Reports
      • Debug Tools Setting Summary Reports
      • TimeQuest Multicorner Timing and Timing Model Datasheet Reports
      • PowerPlay® Power Analyzer Reports
      • Assembler Reports
      • EDA Netlist Writer Reports
      • Managing Reports
        • Manipulating Compilation or Simulation Report Window Output
          • Plan Stage Reports
          • Early Place Stage Reports
          • Place Stage Reports
          • Route Stage Reports
          • Finalize Stage Reports
        • Aligning text:
        • Copying text, charts, table cells, hierarchy entity names and speed performance table rows in reports:
        • Printing the results of a compilation or simulation report:
        • Reordering and hiding columns in the report window:
        • Saving a report window messages or logical memories section:
        • Saving a report table:
        • Selecting reports to print:
        • Include Report Section in Print List Command
        • Compilation Report Command (Processing Menu)
        • Print Command (Report Window)
        • Save Current Report Section As Command
  • Viewing Messages
    • About the Messages window
    • Message Suppression Manager Dialog Box
    • Messages Page (Options Dialog Box)
    • Clear Messages from Window Command (Shortcut Menu)
    • Clear All Flags Command (Shortcut Menu)
    • Clear Flag Command (Shortcut Menu)
    • Flag Message Command (Shortcut Menu)
    • Hide Previous Compilation Messages Command (Shortcut Menu)
    • Load Messages from the Compilation Report (Shortcut Menu)
    • Save Messages Command (Shortcut Menu)
    • Select Text Command (Shortcut Menu)
    • Show All Submessages Command (Shortcut Menu)
    • Clear Sorting Command (Shortcut Menu)
    • Suppress All Flagged Messages Command (Shortcut Menu)
    • Suppress Messages with Matching ID Command (Shortcut Menu)
    • Suppress Messages with Matching Keyword Command (Shortcut Menu)
    • Suppress Message Command (Shortcut Menu)
    • Export Message Flag Rule File Dialog Box
    • Export Message Suppression Rule File Dialog Box
    • Import Message Flag Rule File Dialog Box
    • Import Message Suppression Rule File Dialog Box
    • Suppress by Keyword Dialog Box
  • Compiling Designs
    • Start Compilation Command (Processing Menu)
    • Start Analysis & Synthesis Command (Processing Menu)
    • Start Fitter Commands (Processing Menu)
    • Start Assembler Command (Processing Menu)
  • Compiler Settings
    • Compilation Process Settings Page (Settings Dialog Box)
      • More Compilation Process Settings Dialog Box
    • Device Page (Settings Dialog Box)
      • Board Page (Settings Dialog Box)
    • Device and Pin Options Dialog Box
      • General Page (Device and Pin Options Dialog Box)
        • Delay Entry to User Mode
        • Configuration Clock Source
      • Configuration Page (Device and Pin Options Dialog Box)
      • Programming Files Page (Device and Pin Options Dialog Box)
      • Unused Pins Page (Device and Pin Options Dialog Box)
      • Dual-Purpose Pins Page (Device and Pin Options Dialog Box)
      • Board Trace Model Page (Device and Pin Options Dialog Box)
      • I/O Timing Page (Device and Pin Options Dialog Box)
      • Voltage Page (Device and Pin Options Dialog Box)
      • Error Detection CRC Page (Device and Pin Options Dialog Box)
      • CvP Settings Page (Device and Pin Options Dialog Box)
      • Partial Reconfiguration Page (Device and Pin Options Dialog Box)
    • Compiler Settings Page (Settings Dialog Box)
      • Advanced Synthesis Settings Dialog Box
    • Migration Devices Dialog Box
    • Recommendations Dialog Box
  • Synthesis
    • Start Analysis & Synthesis Command (Processing Menu)
  • Place and Route
    • Start Fitter Commands (Processing Menu)
  • Partial Reconfiguration
    • Design Partitions Window
    • Set As Design Partition Command (Shortcut Menu)
    • Export Design Partition Dialog Box
  • Generating Programming Files
    • Start Assembler Command (Processing Menu)
    • Add JTAG ID Dialog Box
    • Export User-Defined Device Dialog Box
    • Import User Devices Dialog Box
    • Edit Device Dialog Box
    • Add Hex Data Dialog Box
    • Hexadecimal File Options Dialog Box
    • Hardware Setup Dialog Box
    • Open JTAG Chain Log File Dialog Box
    • New CFI Flash Device Dialog Box
    • New Device Dialog Box
    • OpenCore Plus Status Dialog Box
    • PMSF File Properties Dialog Box
    • Select Device Dialog Box
    • Select Flash Device Dialog Box
    • Select New Flash Device Dialog Box
    • SOF Data Properties Dialog Box
    • SOF File Properties Dialog Box
    • Add Hardware Dialog Box
    • Add Server Dialog Box
    • Configure Local JTAG Server Dialog Box
    • Convert Programming Files - Advanced Options Dialog Box
    • Define CFI Flash Device Dialog Box
    • Device's Properties Dialog Box
  • Debugging your Design
    • Debugging with the Signal Tap Logic Analyzer
      • View Page (Signal Tap Logic Analyzer) (Options Dialog Box)
      • Waveform Display Pane (Signal Tap Logic Analyzer)
      • Signal Tap Logic Analyzer Page (Settings Dialog Box)
      • Add Entry Dialog Box
      • Add State Machine Nodes Dialog Box
      • Find Bus Value Dialog Box
      • Import Table Dialog Box
      • Insert Value Dialog Box
      • Add Table Dialog Box
      • Mnemonic Table Setup Dialog Box
      • Object Properties Dialog Box
      • Plug-In Options Dialog Box
      • Print Options Dialog Box (Signal Tap Logic Analyzer)
      • Recreate State Machine Mnemonics Dialog Box
      • Example of Using a Bitwise Object in an Advanced Trigger Condition
      • Example of Using a Comparison Object and Pipelining in an Advanced Trigger Condition
      • Examples of Constructing Advanced Trigger Conditions for the Signal Tap Logic Analyzer
      • Example of Using Data Delay in an Advanced Trigger Condition
      • Example of Using an Edge & Level Detector Object and Logical Conditions in an Advanced Trigger Condition
      • Example of Using a Shift Object in an Advanced Trigger Condition
      • Advanced Trigger Tab (Signal Tap Logic Analyzer)
      • Data Tab (Signal Tap Logic Analyzer)
      • Node List Pane (Signal Tap Logic Analyzer)
      • Object Library Pane (Signal Tap Logic Analyzer)
      • Setup Tab (Signal Tap Logic Analyzer)
      • Signal Configuration Pane (View Menu) (Signal Tap Logic Analyzer)
      • Signal Tap Logic Analyzer Page (Options Dialog Box)
      • State-Based Trigger Flow Tab (Signal Tap Logic Analyzer)
    • Debugging with Signal Probe
      • Start Signal Probe Compilation Command (Processing Menu)
      • Signal Probe Pins Dialog Box
      • Add Signal Probe Pin Dialog Box
    • Debugging with the In-System Memory Content Editor
      • In-System Memory Content Editor Window
    • Debugging with the In-System Sources and Probes Editor
      • Select JTAG Debugging Information File Dialog Box
    • Debugging with the Logic Analyzer Interface
      • Logic Analyzer Interface Editor Window
      • Logic Analyzer Interface Page (Settings Dialog Box)
    • Debugging with the Transceiver Toolkit
      • Load Design Dialog Box
      • Transceiver Toolkit Window
      • Specify Management Clock Dialog Box
      • Report Panel (Transceiver Toolkit)
      • System Console
      • About System Console Window
      • Auto Sweep Panel (Receiver/Transceiver)
      • Control Channel and Control Link Panels
      • Execute Script Dialog Box
  • Optimizing Designs with the Design Space Explorer
    • Launch Design Space Explorer Command (Tools Menu)
  • Optimizing Routing with the Chip Planner
    • Chip Planner Page (Options Dialog Box)
    • Properties Tab (Chip Planner)
    • Tasks Window (Chip Planner)
      • Core Reports
        • Report Routing Utilization Dialog Box
      • Clock Reports
        • Report Used Clock Regions dialog box (Chip Planner)
        • Report Spine Clock Utilization dialog box (Chip Planner)
      • Periphery Reports
        • Report Pins Dialog Box (Chip Planner)
        • Report Placed Pins By I/O Standard
          • Report Resources Dialog Box (Chip Planner)
        • Report HSSI Block Connectivity dialog box (Chip Planner)
      • Partition Reports
        • Report Design Partitions Advanced Dialog Box (Chip Planner)
    • Locate History Pane (Chip Planner)
    • Report Compilation Messages (Chip Planner)
    • Bird's Eye View Window
    • Chip Planner View Menu
      • Report Window (Chip Planner)
        • Properties dialog box (Chip Planner)
      • Show Delays Command (View Menu)
      • Inter-region Bundles Dialog Box
      • Layers Settings Pane
  • Designing with LogicLock® Plus Regions
    • Creating LogicLock® Plus Regions
      • Adding a NewShape to a LogicLock® Plus Region
      • Subtracting Shape from LogicLock® Plus Region
      • Merging LogicLock® Plus Regions
    • LogicLock® Plus Region Properties Dialog Box
      • General tab
      • Shapes tab
    • LogicLock® Plus Routing Region Settings Dialog Box
    • Add Node Dialog Box
    • Export Assignments Dialog Box
    • LogicLock® Plus Regions Window
      • Core-Only
      • Size/State
      • Routing Region
    • Placing Device Resources into LogicLock® Plus Regions
  • Power Estimation and Analysis
    • PowerPlay® Power Analyzer Tool Window
    • Start PowerPlay® Power Analyzer Command (Processing Menu)
    • Add/Edit Power Input File Dialog Box
    • Generate PowerPlay® Early Power Estimator File Command (Project Menu)
    • HPS Power Calulator Dialog Box
    • Select Hierarchy Dialog Box
    • PowerPlay® Power Analyzer Assignment Names
  • Resource Property Editor
    • Resource Property Editor Page (Options Dialog Box)
  • Using the Netlist Viewer
    • Bird's Eye View Command (View Menu)
    • Hide Selection Commands (Shortcut Menu)
    • Filter Commands (Shortcut Menu)
    • Expand to Upper Hierarchy (Shortcut Menu)
    • Generate HDL File Command (Tools Menu)
    • Input Ports List/Ouput Ports List Commands (View Menu)
    • Properties Pane (Netlist Viewers)
    • RTL Viewer Command (Tools Menu)
    • Generate Other Files Dialog Box
    • Technology Map Viewer Command (Tools Menu)
    • Select Bus Index Dialog Box
    • Find Options Dialog Box (Netlist Viewers)
    • Find Pane (Netlist Viewers)
  • Devices and Adapters
    • Devices and Adapters
  • Logic Options Definition
  • Quartus® Prime Scripting Support
    • About Quartus® Prime Scripting
  • Shortcuts
    • Keyboard Shortcuts and Toolbar Buttons
  • Glossary
    • Glossary
  • TCL Commands and Packages
    • quartus::backannotate 1.1
      • get_back_annotation_assignments (::quartus::backannotate)
      • logiclock_back_annotate (::quartus::backannotate)
    • quartus::chip_planner 2.0
      • add_new_cell (::quartus::chip_planner)
      • add_new_io (::quartus::chip_planner)
      • add_usage (::quartus::chip_planner)
      • apply_command (::quartus::chip_planner)
      • check_netlist_and_save (::quartus::chip_planner)
      • check_node (::quartus::chip_planner)
      • close_chip_planner (::quartus::chip_planner)
      • connect_chain (::quartus::chip_planner)
      • convert_signal_probes (::quartus::chip_planner)
      • create_migrated_script (::quartus::chip_planner)
      • delete_sp (::quartus::chip_planner)
      • design_has_ace_support (::quartus::chip_planner)
      • design_has_encrypted_ip (::quartus::chip_planner)
      • disable_sp (::quartus::chip_planner)
      • discard_all_changes (::quartus::chip_planner)
      • discard_node_changes (::quartus::chip_planner)
      • enable_sp (::quartus::chip_planner)
      • export_stack_to (::quartus::chip_planner)
      • get_info_parameters (::quartus::chip_planner)
      • get_iports (::quartus::chip_planner)
      • get_node_by_name (::quartus::chip_planner)
      • get_node_info (::quartus::chip_planner)
      • get_node_loc (::quartus::chip_planner)
      • get_nodes (::quartus::chip_planner)
      • get_oports (::quartus::chip_planner)
      • get_port_by_type (::quartus::chip_planner)
      • get_port_info (::quartus::chip_planner)
      • get_sp_pin_list (::quartus::chip_planner)
      • get_stack (::quartus::chip_planner)
      • get_tile_power_setting (::quartus::chip_planner)
      • list_sps (::quartus::chip_planner)
      • make_ape_connection (::quartus::chip_planner)
      • make_input_port (::quartus::chip_planner)
      • make_output_port (::quartus::chip_planner)
      • make_sp (::quartus::chip_planner)
      • read_netlist (::quartus::chip_planner)
      • remove_ape_connection (::quartus::chip_planner)
      • remove_chain (::quartus::chip_planner)
      • remove_input_port (::quartus::chip_planner)
      • remove_old_cell (::quartus::chip_planner)
      • remove_output_port (::quartus::chip_planner)
      • remove_usage (::quartus::chip_planner)
      • routing_path (::quartus::chip_planner)
      • set_batch_mode (::quartus::chip_planner)
      • set_node_info (::quartus::chip_planner)
      • set_port_info (::quartus::chip_planner)
      • set_tile_power_setting (::quartus::chip_planner)
      • undo_command (::quartus::chip_planner)
      • update_node_loc (::quartus::chip_planner)
    • quartus::database_manager 1.0
      • export_database (::quartus::database_manager)
      • generate_bottom_up_scripts (::quartus::database_manager)
      • import_database (::quartus::database_manager)
    • quartus::design 1.0
      • design::commit_design (::quartus::design)
      • design::create_assignment (::quartus::design)
      • design::delete_assignments (::quartus::design)
      • design::disable_assignments (::quartus::design)
      • design::enable_assignments (::quartus::design)
      • design::export_design (::quartus::design)
      • design::export_partition (::quartus::design)
      • design::get_assignment_info (::quartus::design)
      • design::get_assignment_names (::quartus::design)
      • design::get_assignments (::quartus::design)
      • design::get_entity_names (::quartus::design)
      • design::get_instances (::quartus::design)
      • design::import_design (::quartus::design)
      • design::import_partition (::quartus::design)
      • design::list_valid_snapshot_names (::quartus::design)
      • design::load_design (::quartus::design)
      • design::report_assignments (::quartus::design)
      • design::set_assignment_info (::quartus::design)
    • quartus::device 1.0
      • get_family_list (::quartus::device)
      • get_part_info (::quartus::device)
      • get_part_list (::quartus::device)
      • report_device_info (::quartus::device)
      • report_family_info (::quartus::device)
      • report_part_info (::quartus::device)
    • quartus::external_memif_toolkit 1.0
      • apply_setting (::quartus::external_memif_toolkit)
      • calibrate_termination (::quartus::external_memif_toolkit)
      • configure_driver (::quartus::external_memif_toolkit)
      • create_connection_report (::quartus::external_memif_toolkit)
      • create_toolkit_report (::quartus::external_memif_toolkit)
      • driver_margining (::quartus::external_memif_toolkit)
      • establish_connection (::quartus::external_memif_toolkit)
      • generate_eye_diagram (::quartus::external_memif_toolkit)
      • get_connection_commands (::quartus::external_memif_toolkit)
      • get_connection_info (::quartus::external_memif_toolkit)
      • get_connection_interfaces (::quartus::external_memif_toolkit)
      • get_connection_report_info (::quartus::external_memif_toolkit)
      • get_connection_report_types (::quartus::external_memif_toolkit)
      • get_connection_types (::quartus::external_memif_toolkit)
      • get_connections (::quartus::external_memif_toolkit)
      • get_device_names (::quartus::external_memif_toolkit)
      • get_hardware_names (::quartus::external_memif_toolkit)
      • get_setting_types (::quartus::external_memif_toolkit)
      • get_toolkit_report_types (::quartus::external_memif_toolkit)
      • initialize_connections (::quartus::external_memif_toolkit)
      • link_project_to_device (::quartus::external_memif_toolkit)
      • read_setting (::quartus::external_memif_toolkit)
      • reindex_connections (::quartus::external_memif_toolkit)
      • reset_tg2 (::quartus::external_memif_toolkit)
      • run_connection_command (::quartus::external_memif_toolkit)
      • set_active_interface (::quartus::external_memif_toolkit)
      • set_stress_pattern (::quartus::external_memif_toolkit)
      • terminate_connection (::quartus::external_memif_toolkit)
      • terminate_connections (::quartus::external_memif_toolkit)
      • unlink_project_from_device (::quartus::external_memif_toolkit)
      • write_connection_target_report (::quartus::external_memif_toolkit)
    • quartus::fif 1.0
      • check (::quartus::fif)
      • dump (::quartus::fif)
      • dump_cram_frame (::quartus::fif)
      • dump_mem (::quartus::fif)
      • dump_pr_bitstream (::quartus::fif)
      • generate (::quartus::fif)
      • get_frame_count (::quartus::fif)
      • get_frame_size (::quartus::fif)
      • get_sensitive_location (::quartus::fif)
      • setup (::quartus::fif)
      • terminate (::quartus::fif)
    • quartus::flow 1.1
      • delete_netlist (::quartus::flow)
      • execute_flow (::quartus::flow)
      • execute_module (::quartus::flow)
      • get_flow_templates (::quartus::flow)
      • netlist_exists (::quartus::flow)
      • write_flow_finished (::quartus::flow)
      • write_flow_started (::quartus::flow)
      • write_flow_template (::quartus::flow)
    • quartus::incremental_compilation 1.1
      • auto_partition_design (::quartus::incremental_compilation)
      • boundary_optimizations (::quartus::incremental_compilation)
      • create_partition (::quartus::incremental_compilation)
      • delete_all_logiclock (::quartus::incremental_compilation)
      • delete_all_partitions (::quartus::incremental_compilation)
      • delete_logiclock (::quartus::incremental_compilation)
      • delete_partition (::quartus::incremental_compilation)
      • export_partition (::quartus::incremental_compilation)
      • export_persona (::quartus::incremental_compilation)
      • generate_qxp_report (::quartus::incremental_compilation)
      • get_exact_placement_changed_nodes (::quartus::incremental_compilation)
      • get_logiclock (::quartus::incremental_compilation)
      • get_logiclock_contents (::quartus::incremental_compilation)
      • get_nodes_changed_before_cloud_expansion (::quartus::incremental_compilation)
      • get_nodes_changed_in_cloud_expansion (::quartus::incremental_compilation)
      • get_output_persona_filename (::quartus::incremental_compilation)
      • get_partition (::quartus::incremental_compilation)
      • get_partition_file_list (::quartus::incremental_compilation)
      • get_placement_changed_nodes (::quartus::incremental_compilation)
      • get_placement_partially_preserved_nodes (::quartus::incremental_compilation)
      • get_routing_changed_nodes (::quartus::incremental_compilation)
      • import_partition (::quartus::incremental_compilation)
      • import_persona (::quartus::incremental_compilation)
      • merge_partitions (::quartus::incremental_compilation)
      • partition_delete_netlists (::quartus::incremental_compilation)
      • partition_netlist_exists (::quartus::incremental_compilation)
      • set_logiclock (::quartus::incremental_compilation)
      • set_logiclock_contents (::quartus::incremental_compilation)
      • set_partition (::quartus::incremental_compilation)
      • split_partition (::quartus::incremental_compilation)
    • quartus::insystem_memory_edit 1.0
      • begin_memory_edit (::quartus::insystem_memory_edit)
      • end_memory_edit (::quartus::insystem_memory_edit)
      • get_editable_mem_instances (::quartus::insystem_memory_edit)
      • read_content_from_memory (::quartus::insystem_memory_edit)
      • save_content_from_memory_to_file (::quartus::insystem_memory_edit)
      • update_content_to_memory_from_file (::quartus::insystem_memory_edit)
      • write_content_to_memory (::quartus::insystem_memory_edit)
    • quartus::insystem_source_probe 1.0
      • end_insystem_source_probe (::quartus::insystem_source_probe)
      • get_insystem_source_probe_instance_info (::quartus::insystem_source_probe)
      • read_probe_data (::quartus::insystem_source_probe)
      • read_source_data (::quartus::insystem_source_probe)
      • start_insystem_source_probe (::quartus::insystem_source_probe)
      • write_source_data (::quartus::insystem_source_probe)
    • quartus::interactive_synthesis 1.0
      • analyze_files (::quartus::interactive_synthesis)
      • check_rtl_connections (::quartus::interactive_synthesis)
      • dissolve_rtl_partition (::quartus::interactive_synthesis)
      • elaborate (::quartus::interactive_synthesis)
      • get_entities (::quartus::interactive_synthesis)
      • get_rtl_partition_name (::quartus::interactive_synthesis)
      • get_rtl_partitions (::quartus::interactive_synthesis)
      • link_rtl_design (::quartus::interactive_synthesis)
      • print_ipxact (::quartus::interactive_synthesis)
      • report_rtl_assignments (::quartus::interactive_synthesis)
      • report_rtl_parameters (::quartus::interactive_synthesis)
      • report_rtl_stats (::quartus::interactive_synthesis)
      • reset_rtl_design (::quartus::interactive_synthesis)
      • save_rtl_design (::quartus::interactive_synthesis)
      • synthesize (::quartus::interactive_synthesis)
      • uniquify (::quartus::interactive_synthesis)
      • write_rtl_report (::quartus::interactive_synthesis)
    • quartus::ipgen 1.0
      • clear_ip_generation_dirs (::quartus::ipgen)
      • generate_ip_file (::quartus::ipgen)
      • generate_project_ip_files (::quartus::ipgen)
      • get_project_ip_files (::quartus::ipgen)
    • quartus::iptclgen 1.0
      • compute_pll (::quartus::iptclgen)
      • generate_vhdl_simgen_model (::quartus::iptclgen)
      • parse_hdl (::quartus::iptclgen)
      • parse_tcl (::quartus::iptclgen)
    • quartus::jtag 1.0
      • close_device (::quartus::jtag)
      • device_dr_shift (::quartus::jtag)
      • device_ir_shift (::quartus::jtag)
      • device_lock (::quartus::jtag)
      • device_run_test_idle (::quartus::jtag)
      • device_unlock (::quartus::jtag)
      • device_virtual_dr_shift (::quartus::jtag)
      • device_virtual_ir_shift (::quartus::jtag)
      • get_device_names (::quartus::jtag)
      • get_hardware_names (::quartus::jtag)
      • open_device (::quartus::jtag)
    • quartus::logic_analyzer_interface 1.0
      • begin_logic_analyzer_interface_control (::quartus::logic_analyzer_interface)
      • change_bank_to_output_pin (::quartus::logic_analyzer_interface)
      • end_logic_analyzer_interface_control (::quartus::logic_analyzer_interface)
      • get_current_state_of_output_pin (::quartus::logic_analyzer_interface)
      • tristate_output_pin (::quartus::logic_analyzer_interface)
    • quartus::misc 1.0
      • checksum (::quartus::misc)
      • disable_natural_bus_naming (::quartus::misc)
      • enable_natural_bus_naming (::quartus::misc)
      • escape_brackets (::quartus::misc)
      • foreach_in_collection (::quartus::misc)
      • get_collection_size (::quartus::misc)
      • get_environment_info (::quartus::misc)
      • init_tk (::quartus::misc)
      • load (::quartus::misc)
      • load_package (::quartus::misc)
      • post_message (::quartus::misc)
      • qerror (::quartus::misc)
      • qexec (::quartus::misc)
      • qexit (::quartus::misc)
      • stopwatch (::quartus::misc)
    • quartus::names 1.0
      • get_assignment (::quartus::names)
      • set_assignment (::quartus::names)
    • quartus::periph 1.0
      • blueprint::initialize (::quartus::periph)
      • blueprint::shutdown (::quartus::periph)
      • periph::check_plan (::quartus::periph)
      • periph::get_cell_info (::quartus::periph)
      • periph::get_cells (::quartus::periph)
      • periph::get_location_info (::quartus::periph)
      • periph::get_placement_info (::quartus::periph)
      • periph::get_placements (::quartus::periph)
      • periph::load_floorplan (::quartus::periph)
      • periph::place_cells (::quartus::periph)
      • periph::remove_invalid_reports (::quartus::periph)
      • periph::report_all (::quartus::periph)
      • periph::report_cell_connectivity (::quartus::periph)
      • periph::report_cell_placement_reasons (::quartus::periph)
      • periph::report_cells (::quartus::periph)
      • periph::report_clocks (::quartus::periph)
      • periph::report_legal_cell_locations (::quartus::periph)
      • periph::report_location_types (::quartus::periph)
      • periph::report_locations (::quartus::periph)
      • periph::report_regions (::quartus::periph)
      • periph::report_summary (::quartus::periph)
      • periph::reset_plan (::quartus::periph)
      • periph::save_floorplan (::quartus::periph)
      • periph::set_clock_type (::quartus::periph)
      • periph::undo_last_placement (::quartus::periph)
      • periph::unplace_cells (::quartus::periph)
      • periph::update_plan (::quartus::periph)
      • periph::write_plan (::quartus::periph)
    • quartus::project_tedq 1.0
    • quartus::project_ui 1.0
      • assignment_group (::quartus::project_ui)
      • create_revision (::quartus::project_ui)
      • delete_revision (::quartus::project_ui)
      • execute_assignment_batch (::quartus::project_ui)
      • export_assignments (::quartus::project_ui)
      • get_all_assignment_names (::quartus::project_ui)
      • get_all_assignments (::quartus::project_ui)
      • get_all_global_assignments (::quartus::project_ui)
      • get_all_instance_assignments (::quartus::project_ui)
      • get_all_parameters (::quartus::project_ui)
      • get_all_quartus_defaults (::quartus::project_ui)
      • get_all_user_option_names (::quartus::project_ui)
      • get_assignment_info (::quartus::project_ui)
      • get_assignment_name_info (::quartus::project_ui)
      • get_current_project (::quartus::project_ui)
      • get_current_revision (::quartus::project_ui)
      • get_global_assignment (::quartus::project_ui)
      • get_instance_assignment (::quartus::project_ui)
      • get_location_assignment (::quartus::project_ui)
      • get_name_info (::quartus::project_ui)
      • get_names (::quartus::project_ui)
      • get_parameter (::quartus::project_ui)
      • get_project_directory (::quartus::project_ui)
      • get_project_revisions (::quartus::project_ui)
      • get_top_level_entity (::quartus::project_ui)
      • get_user_option (::quartus::project_ui)
      • is_project_open (::quartus::project_ui)
      • project_archive (::quartus::project_ui)
      • project_close (::quartus::project_ui)
      • project_exists (::quartus::project_ui)
      • project_new (::quartus::project_ui)
      • project_open (::quartus::project_ui)
      • project_restore (::quartus::project_ui)
      • remove_all_global_assignments (::quartus::project_ui)
      • remove_all_instance_assignments (::quartus::project_ui)
      • remove_all_parameters (::quartus::project_ui)
      • resolve_file_path (::quartus::project_ui)
      • revision_exists (::quartus::project_ui)
      • set_current_revision (::quartus::project_ui)
      • set_global_assignment (::quartus::project_ui)
      • set_instance_assignment (::quartus::project_ui)
      • set_io_assignment (::quartus::project_ui)
      • set_location_assignment (::quartus::project_ui)
      • set_parameter (::quartus::project_ui)
      • set_power_file_assignment (::quartus::project_ui)
      • set_user_option (::quartus::project_ui)
      • test_assignment_trait (::quartus::project_ui)
    • quartus::project 6.0
      • assignment_group (::quartus::project)
      • create_revision (::quartus::project)
      • delete_revision (::quartus::project)
      • execute_assignment_batch (::quartus::project)
      • export_assignments (::quartus::project)
      • get_all_assignment_names (::quartus::project)
      • get_all_assignments (::quartus::project)
      • get_all_global_assignments (::quartus::project)
      • get_all_instance_assignments (::quartus::project)
      • get_all_parameters (::quartus::project)
      • get_all_quartus_defaults (::quartus::project)
      • get_all_user_option_names (::quartus::project)
      • get_assignment_info (::quartus::project)
      • get_assignment_name_info (::quartus::project)
      • get_current_project (::quartus::project)
      • get_current_revision (::quartus::project)
      • get_database_version (::quartus::project)
      • get_global_assignment (::quartus::project)
      • get_instance_assignment (::quartus::project)
      • get_location_assignment (::quartus::project)
      • get_name_info (::quartus::project)
      • get_names (::quartus::project)
      • get_parameter (::quartus::project)
      • get_project_directory (::quartus::project)
      • get_project_revisions (::quartus::project)
      • get_top_level_entity (::quartus::project)
      • get_user_option (::quartus::project)
      • is_database_version_compatible (::quartus::project)
      • is_fitter_in_qhd_mode (::quartus::project)
      • is_project_open (::quartus::project)
      • project_archive (::quartus::project)
      • project_clean (::quartus::project)
      • project_close (::quartus::project)
      • project_exists (::quartus::project)
      • project_new (::quartus::project)
      • project_open (::quartus::project)
      • project_restore (::quartus::project)
      • remove_all_global_assignments (::quartus::project)
      • remove_all_instance_assignments (::quartus::project)
      • remove_all_parameters (::quartus::project)
      • resolve_file_path (::quartus::project)
      • revision_exists (::quartus::project)
      • set_current_revision (::quartus::project)
      • set_global_assignment (::quartus::project)
      • set_high_effort_fmax_optimization_assignments (::quartus::project)
      • set_instance_assignment (::quartus::project)
      • set_io_assignment (::quartus::project)
      • set_location_assignment (::quartus::project)
      • set_parameter (::quartus::project)
      • set_power_file_assignment (::quartus::project)
      • set_user_option (::quartus::project)
      • test_assignment_trait (::quartus::project)
    • quartus::qshm 1.0
      • qshm_connect_to_quartus (::quartus::qshm)
      • qshm_disconnect_from_quartus (::quartus::qshm)
      • qshm_dispose_client (::quartus::qshm)
      • qshm_get_hub_key_prefix (::quartus::qshm)
      • qshm_get_parent_hub_key (::quartus::qshm)
      • qshm_obtain_client (::quartus::qshm)
      • qshm_send_request (::quartus::qshm)
      • qshm_send_server_state_query (::quartus::qshm)
      • qshm_set_context (::quartus::qshm)
    • quartus::report 2.1
      • add_row_to_table (::quartus::report)
      • create_report_panel (::quartus::report)
      • delete_report_panel (::quartus::report)
      • get_fitter_resource_usage (::quartus::report)
      • get_number_of_columns (::quartus::report)
      • get_number_of_rows (::quartus::report)
      • get_report_panel_column_index (::quartus::report)
      • get_report_panel_data (::quartus::report)
      • get_report_panel_id (::quartus::report)
      • get_report_panel_names (::quartus::report)
      • get_report_panel_row (::quartus::report)
      • get_report_panel_row_index (::quartus::report)
      • load_report (::quartus::report)
      • read_xml_report (::quartus::report)
      • refresh_report_window (::quartus::report)
      • save_report_database (::quartus::report)
      • unload_report (::quartus::report)
      • write_report_panel (::quartus::report)
      • write_xml_report (::quartus::report)
    • quartus::rtl 1.0
      • get_rtl_cell_info (::quartus::rtl)
      • get_rtl_cells (::quartus::rtl)
      • get_rtl_fanins (::quartus::rtl)
      • get_rtl_fanouts (::quartus::rtl)
      • get_rtl_pin_info (::quartus::rtl)
      • get_rtl_pins (::quartus::rtl)
      • load_rtl_netlist (::quartus::rtl)
      • report_atom_node_summary (::quartus::rtl)
      • report_rtl_pin_summary (::quartus::rtl)
      • unload_rtl_netlist (::quartus::rtl)
    • quartus::rtm 1.0
      • rtm_in_post_fit_retimer (::quartus::rtm)
      • rtm_retime (::quartus::rtm)
    • quartus::sdc_ext 1.0
      • derive_clock_uncertainty (::quartus::sdc_ext)
      • derive_pll_clocks (::quartus::sdc_ext)
      • get_active_clocks (::quartus::sdc_ext)
      • get_assignment_groups (::quartus::sdc_ext)
      • get_fanins (::quartus::sdc_ext)
      • get_fanouts (::quartus::sdc_ext)
      • get_keepers (::quartus::sdc_ext)
      • get_nodes (::quartus::sdc_ext)
      • get_partitions (::quartus::sdc_ext)
      • get_registers (::quartus::sdc_ext)
      • remove_annotated_delay (::quartus::sdc_ext)
      • remove_clock (::quartus::sdc_ext)
      • reset_timing_derate (::quartus::sdc_ext)
      • set_active_clocks (::quartus::sdc_ext)
      • set_annotated_delay (::quartus::sdc_ext)
      • set_max_skew (::quartus::sdc_ext)
      • set_net_delay (::quartus::sdc_ext)
      • set_scc_mode (::quartus::sdc_ext)
      • set_time_format (::quartus::sdc_ext)
      • set_timing_derate (::quartus::sdc_ext)
    • quartus::sdc 1.5
      • all_clocks (::quartus::sdc)
      • all_inputs (::quartus::sdc)
      • all_outputs (::quartus::sdc)
      • all_registers (::quartus::sdc)
      • create_clock (::quartus::sdc)
      • create_generated_clock (::quartus::sdc)
      • derive_clocks (::quartus::sdc)
      • get_cells (::quartus::sdc)
      • get_clocks (::quartus::sdc)
      • get_nets (::quartus::sdc)
      • get_pins (::quartus::sdc)
      • get_ports (::quartus::sdc)
      • remove_clock_groups (::quartus::sdc)
      • remove_clock_latency (::quartus::sdc)
      • remove_clock_uncertainty (::quartus::sdc)
      • remove_disable_timing (::quartus::sdc)
      • remove_input_delay (::quartus::sdc)
      • remove_output_delay (::quartus::sdc)
      • reset_design (::quartus::sdc)
      • set_clock_groups (::quartus::sdc)
      • set_clock_latency (::quartus::sdc)
      • set_clock_uncertainty (::quartus::sdc)
      • set_disable_timing (::quartus::sdc)
      • set_false_path (::quartus::sdc)
      • set_input_delay (::quartus::sdc)
      • set_input_transition (::quartus::sdc)
      • set_max_delay (::quartus::sdc)
      • set_min_delay (::quartus::sdc)
      • set_multicycle_path (::quartus::sdc)
      • set_output_delay (::quartus::sdc)
    • quartus::sta 1.0
      • add_to_collection (::quartus::sta)
      • check_timing (::quartus::sta)
      • create_report_histogram (::quartus::sta)
      • create_slack_histogram (::quartus::sta)
      • create_timing_netlist (::quartus::sta)
      • create_timing_summary (::quartus::sta)
      • delete_sta_collection (::quartus::sta)
      • delete_timing_netlist (::quartus::sta)
      • enable_ccpp_removal (::quartus::sta)
      • enable_sdc_extension_collections (::quartus::sta)
      • get_available_operating_conditions (::quartus::sta)
      • get_cell_info (::quartus::sta)
      • get_clock_domain_info (::quartus::sta)
      • get_clock_fmax_info (::quartus::sta)
      • get_clock_info (::quartus::sta)
      • get_datasheet (::quartus::sta)
      • get_default_sdc_file_names (::quartus::sta)
      • get_edge_info (::quartus::sta)
      • get_edge_slacks (::quartus::sta)
      • get_entity_instances (::quartus::sta)
      • get_min_pulse_width (::quartus::sta)
      • get_net_info (::quartus::sta)
      • get_node_info (::quartus::sta)
      • get_object_info (::quartus::sta)
      • get_operating_conditions (::quartus::sta)
      • get_operating_conditions_info (::quartus::sta)
      • get_partition_info (::quartus::sta)
      • get_path (::quartus::sta)
      • get_path_info (::quartus::sta)
      • get_pin_info (::quartus::sta)
      • get_point_info (::quartus::sta)
      • get_port_info (::quartus::sta)
      • get_register_info (::quartus::sta)
      • get_timing_paths (::quartus::sta)
      • locate (::quartus::sta)
      • query_collection (::quartus::sta)
      • read_sdc (::quartus::sta)
      • register_delete_timing_netlist_callback (::quartus::sta)
      • remove_from_collection (::quartus::sta)
      • report_advanced_io_timing (::quartus::sta)
      • report_bottleneck (::quartus::sta)
      • report_cdc_viewer (::quartus::sta)
      • report_clock_fmax_summary (::quartus::sta)
      • report_clock_transfers (::quartus::sta)
      • report_clocks (::quartus::sta)
      • report_datasheet (::quartus::sta)
      • report_ddr (::quartus::sta)
      • report_exceptions (::quartus::sta)
      • report_ini_usage (::quartus::sta)
      • report_max_skew (::quartus::sta)
      • report_metastability (::quartus::sta)
      • report_min_pulse_width (::quartus::sta)
      • report_net_delay (::quartus::sta)
      • report_net_timing (::quartus::sta)
      • report_partitions (::quartus::sta)
      • report_path (::quartus::sta)
      • report_rskm (::quartus::sta)
      • report_sdc (::quartus::sta)
      • report_skew (::quartus::sta)
      • report_tccs (::quartus::sta)
      • report_timing (::quartus::sta)
      • report_timing_tree (::quartus::sta)
      • report_ucp (::quartus::sta)
      • set_operating_conditions (::quartus::sta)
      • timing_netlist_exist (::quartus::sta)
      • update_timing_netlist (::quartus::sta)
      • use_timequest_style_escaping (::quartus::sta)
      • write_sdc (::quartus::sta)
    • quartus::stp 1.0
      • close_session (::quartus::stp)
      • export_data_log (::quartus::stp)
      • open_session (::quartus::stp)
      • run (::quartus::stp)
      • run_multiple_end (::quartus::stp)
      • run_multiple_start (::quartus::stp)
      • stop (::quartus::stp)
    • quartus::synthesis_report 1.0
      • get_parameter_settings (::quartus::synthesis_report)
      • get_parameter_settings_info (::quartus::synthesis_report)
      • get_source_assignment_info (::quartus::synthesis_report)
      • get_source_assignments (::quartus::synthesis_report)
      • report_parameter_settings (::quartus::synthesis_report)
      • report_removed_registers (::quartus::synthesis_report)
      • report_resource_utilization (::quartus::synthesis_report)
      • report_source_assignments (::quartus::synthesis_report)
    • quartus::tdc 1.0
      • is_post_route (::quartus::tdc)
  • List of Messages