Performing a Gate-Level Simulation with the Riviera-PRO Software
You can use the Aldec Riviera-PRO software to perform a gate-level (post-fit) simulation of a VHDL or Verilog HDL design that contains Intel-specific components.
Note: The Riviera-PRO software not only has its own native command-line commands, but
also supports ModelSim command-line commands. In the following steps, the ModelSim
commands are the
commands that start with "v", such as
vlib
.
To run the simulation until the end, leave out the <running time>
argument.
Note:
Use the command transcript file<file_name>
to record messages.
Note: For more information about using EDA simulators, refer to Aldec Active-HDL and Riviera-PRO
Support in the
Quartus® Prime Handbook.