SRS Summary

Base Address: 0x10808200


Register Address Offset	Bit Fields
`i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`
`SRS00` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SAAR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SAAR` `RW 0x0`
`SRS01` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BCCT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`	`SDMABB` `RW 0x0`			`TBS` `RW 0x0`
`SRS02` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ARG1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ARG1` `RW 0x0`
`SRS03` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_15` `RO 0x0`		`CIDX` `RW 0x0`						`CT` `RW 0x0`		`DPS` `RW 0x0`	`CICE` `RW 0x0`	`CRCCE` `RW 0x0`	`SCF` `RW 0x0`	`RTS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_8` `RO 0x0`							`RID` `RW 0x0`	`RECE` `RW 0x0`	`RECT` `RW 0x0`	`MSBS` `RW 0x0`	`DTDS` `RW 0x0`	`ACE` `RW 0x0`		`BCE` `RW 0x0`	`DMAE` `RW 0x0`
`SRS04` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESP0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESP0` `RO 0x0`
`SRS05` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESP1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESP1` `RO 0x0`
`SRS06` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESP2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESP2` `RO 0x0`
`SRS07` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESP3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESP3` `RO 0x0`
`SRS08` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BDP` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BDP` `RW 0x0`
`SRS09` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_17` `RO 0x0`			`SCMDS` `RO 0x0`	`CNIBE` `RO 0x0`	`LVSIRSLT` `RO 0x0`	`Reserved_14` `RO 0x0`	`CMDSL` `RO 0x0`	`DATSL1` `RO 0x0`				`WPSL` `RO 0x0`	`CDSL` `RO 0x0`	`CSS` `RO 0x0`	`CI` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_8` `RO 0x0`				`BRE` `RO 0x0`	`BWE` `RO 0x0`	`RTA` `RO 0x0`	`WTA` `RO 0x0`	`DATSL2` `RO 0x0`				`Reserved_3` `RO 0x0`	`DLA` `RO 0x0`	`CIDAT` `RO 0x0`	`CICMD` `RO 0x0`
`SRS10` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_16` `RO 0x0`					`WORM` `RW 0x0`	`WOIS` `RW 0x0`	`WOIQ` `RW 0x0`	`Reserved_13` `RO 0x0`				`IBG` `RW 0x0`	`RWC` `RW 0x0`	`CREQ` `RW 0x0`	`SBGR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_9` `RO 0x0`				`BVS` `RW 0x0`			`BP` `RW 0x0`	`CDSS` `RW 0x0`	`CDTL` `RW 0x0`	`EDTW` `RW 0x0`	`DMASEL` `RW 0x0`		`HSE` `RW 0x0`	`DTW` `RW 0x0`	`LEDC` `RW 0x0`
`SRS11` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`					`SRDAT` `RW 0x0`	`SRCMD` `RW 0x0`	`SRFA` `RW 0x0`	`Reserved_6` `RO 0x0`				`DTCV` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SDCFSL` `RW 0x0`								`SDCFSH` `RW 0x0`		`Reserved_3` `RO 0x0`			`SDCE` `RW 0x0`	`ICS` `RO 0x0`	`ICE` `RW 0x0`
`SRS12` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_23` `RO 0x0`				`ERSP` `RW 0x0`	`Reserved_22` `RO 0x0`	`EADMA` `RW 0x0`	`EAC` `RW 0x0`	`ECL` `RW 0x0`	`EDEB` `RW 0x0`	`EDCRC` `RW 0x0`	`EDT` `RW 0x0`	`ECI` `RW 0x0`	`ECEB` `RW 0x0`	`ECCRC` `RW 0x0`	`ECT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EINT` `RO 0x0`	`CQINT` `RO 0x0`	`FXE` `RO 0x0`	`Reserved_9` `RO 0x0`				`CINT` `RO 0x0`	`CR` `RW 0x0`	`CIN` `RW 0x0`	`BRR` `RW 0x0`	`BWR` `RW 0x0`	`DMAINT` `RW 0x0`	`BGE` `RW 0x0`	`TC` `RW 0x0`	`CC` `RW 0x0`
`SRS13` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_22` `RO 0x0`				`ERSP_SE` `RW 0x0`	`Reserved_21` `RO 0x0`	`EADMA_SE` `RW 0x0`	`EAC_SE` `RW 0x0`	`ECL_SE` `RW 0x0`	`EDEB_SE` `RW 0x0`	`EDCRC_SE` `RW 0x0`	`EDT_SE` `RW 0x0`	`ECI_SE` `RW 0x0`	`ECEB_SE` `RW 0x0`	`ECCRC_SE` `RW 0x0`	`ECT_SE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_11` `RO 0x0`	`CQINT_SE` `RW 0x0`	`FXE_SE` `RW 0x0`	`Reserved_9` `RO 0x0`				`CINT_SE` `RW 0x0`	`CR_SE` `RW 0x0`	`CIN_SE` `RW 0x0`	`BRR_SE` `RW 0x0`	`BWR_SE` `RW 0x0`	`DMAINT_SE` `RW 0x0`	`BGE_SE` `RW 0x0`	`TC_SE` `RW 0x0`	`CC_SE` `RW 0x0`
`SRS14` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_22` `RO 0x0`				`ERSP_IE` `RW 0x0`	`Reserved_21` `RO 0x0`	`EADMA_IE` `RW 0x0`	`EAC_IE` `RW 0x0`	`ECL_IE` `RW 0x0`	`EDEB_IE` `RW 0x0`	`EDCRC_IE` `RW 0x0`	`EDT_IE` `RW 0x0`	`ECI_IE` `RW 0x0`	`ECEB_IE` `RW 0x0`	`ECCRC_IE` `RW 0x0`	`ECT_IE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_11` `RO 0x0`	`CQINT_IE` `RW 0x0`	`FXE_IE` `RW 0x0`	`Reserved_9` `RO 0x0`				`CINT_IE` `RW 0x0`	`CR_IE` `RW 0x0`	`CIN_IE` `RW 0x0`	`BRR_IE` `RW 0x0`	`BWR_IE` `RW 0x0`	`DMAINT_IE` `RW 0x0`	`BGE_IE` `RW 0x0`	`TC_IE` `RW 0x0`	`CC_IE` `RW 0x0`
`SRS15` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PVE` `RW 0x0`	`Reserved_17` `RO 0x0`	`A64B` `RW 0x0`	`HV4E` `RW 0x0`	`CMD23E` `RW 0x0`	`ADMA2LM` `RW 0x0`	`Reserved_13` `RO 0x0`	`LVSIEXEC` `RW 0x0`	`SCS` `RW 0x0`	`EXTNG` `RW 0x0`	`DSS` `RW 0x0`		`V18SE` `RW 0x0`	`UMS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`								`CNIACE` `RO 0x0`	`Reserved_6` `RO 0x0`	`ACRE` `RO 0x0`	`ACIE` `RO 0x0`	`ACEBE` `RO 0x0`	`ACCE` `RO 0x0`	`ACTE` `RO 0x0`	`ACNE` `RO 0x0`
`SRS16` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SLT` `RO 0x0`		`AIS` `RO 0x0`	`A64SV3` `RO 0x1`	`A64SV4` `RO 0x1`	`VS18` `RO 0x1`	`VS30` `RO 0x1`	`VS33` `RO 0x1`	`SRS` `RO 0x0`	`DMAS` `RO 0x1`	`HSS` `RO 0x1`	`ADMA1S` `RO 0x0`	`ADMA2S` `RO 0x1`	`EDS8` `RO 0x0`	`MBL` `RO 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BCSDCLK` `RO 0xC8`								`TCU` `RO 0x1`	`Reserved_1` `RO 0x0`	`TCF` `RO 0x32`
`SRS17` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LVSH` `RO 0x1`	`Reserved_13` `RO 0x0`		`VDD2S` `RO 0x0`	`ADMA3SUP` `RO 0x1`	`Reserved_11` `RO 0x0`			`CLKMPR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RTNGM` `RO 0x0`		`UTSM50` `RO 0x0`	`Reserved_8` `RO 0x0`	`RTNGCNT` `RO 0x0`				`Reserved_7` `RO 0x0`	`DRVD` `RO 0x1`	`DRVC` `RO 0x1`	`DRVA` `RO 0x1`	`UHSII` `RO 0x0`	`DDR50` `RO 0x1`	`SDR104` `RO 0x1`	`SDR50` `RO 0x1`
`SRS18` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`								`MC18` `RO 0x20`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MC30` `RO 0x20`								`MC33` `RO 0x20`
`SRS19` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`MC18V2` `RO 0x20`
`SRS20` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_18` `RO 0x0`				`ERESP_FE` `WO 0x0`	`ETUNE_FE` `WO 0x0`	`EADMA_FE` `WO 0x0`	`EAC_FE` `WO 0x0`	`ECL_FE` `WO 0x0`	`EDEB_FE` `WO 0x0`	`EDCRC_FE` `WO 0x0`	`EDT_FE` `WO 0x0`	`ECI_FE` `WO 0x0`	`ECEB_FE` `WO 0x0`	`ECCRC_FE` `WO 0x0`	`ECT_FE` `WO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_6` `RO 0x0`								`CNIACE_FE` `WO 0x0`	`Reserved_5` `RO 0x0`		`ACIE_FE` `WO 0x0`	`ACEBE_FE` `WO 0x0`	`ACCE_FE` `WO 0x0`	`ACTE_FE` `WO 0x0`	`ACNE_FE` `WO 0x0`
`SRS21` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`													`EADMAL` `RO 0x0`	`EADMAS` `RO 0x0`
`SRS22` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DMASA1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DMASA1` `RW 0x0`
`SRS23` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DMASA2` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DMASA2` `RW 0x0`
`SRS24` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SRS24_DSSPV_31_30` `RO 0x0`		`Reserved_1` `RO 0x0`				`SRS24_SDCFSPV_25_16` `RO 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_0` `RO 0x0`
`SRS25` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SRS25_DSSPV_31_30` `RO 0x0`		`Reserved_3` `RO 0x0`				`SRS25_SDCFSPV_25_16` `RO 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SRS25_DSSPV_15_14` `RO 0x0`		`Reserved_1` `RO 0x0`				`SRS25_SDCFSPV_09_00` `RO 0x2`
`SRS26` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SRS26_DSSPV_31_30` `RO 0x0`		`Reserved_4` `RO 0x0`				`SRS26_SDCFSPV_25_16` `RO 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SRS26_DSSPV_15_14` `RO 0x0`		`Reserved_2` `RO 0x0`			`SRS26_CGSPV_10` `RO 0x0`	`SRS26_SDCFSPV_09_00` `RO 0x2`
`SRS27` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SRS27_DSSPV_31_30` `RO 0x0`		`Reserved_3` `RO 0x0`				`SRS27_SDCFSPV_25_16` `RO 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SRS27_DSSPV_15_14` `RO 0x0`		`Reserved_1` `RO 0x0`				`SRS27_SDCFSPV_09_00` `RO 0x0`
`SRS30` `0x120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADMA3ID1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADMA3ID1` `RW 0x0`
`SRS31` `0x124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADMA3ID2` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADMA3ID2` `RW 0x0`