SRS15 

         SRS15 - Host Control #2 / Auto CMD Error Status
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x1080823C

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PVE

RW 0x0

Reserved_17

RO 0x0

A64B

RW 0x0

HV4E

RW 0x0

CMD23E

RW 0x0

ADMA2LM

RW 0x0

Reserved_13

RO 0x0

LVSIEXEC

RW 0x0

SCS

RW 0x0

EXTNG

RW 0x0

DSS

RW 0x0

V18SE

RW 0x0

UMS

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_7

RO 0x0

CNIACE

RO 0x0

Reserved_6

RO 0x0

ACRE

RO 0x0

ACIE

RO 0x0

ACEBE

RO 0x0

ACCE

RO 0x0

ACTE

RO 0x0

ACNE

RO 0x0

SRS15 Fields

Bit Name Description Access Reset
31 PVE 
              PVE - Preset Value Enable\n
              Setting this bit to 1 triggers an automatically update of SRS11.SDCFSL, SRS11.SDCFSH, SRS11.CGS, SRS15.DSS registers by the host.
              Values for an update are taken from SRS24 - SRS27 and depends on SRS15.UMS.
RW 0x0
30 Reserved_17 
Reserved bitfield added by Magillem
 RO 0x0
29 A64B 
              A64B - 64-bit Addressing\n
              Specifies the addressing mode for DMA ending. This field is ignored when SRS15.HV4E=0.\n
              0 - 32-bit addressing\n
              1 - 64-bit addressing
RW 0x0
28 HV4E 
              HV4E - Host Version 4.00 Enable\n
              Selects backward (SD Host 3.00 Version) compatibility mode or SD Host 4.00 Version mode.\n
              0 - Version 3.00\n
              1 - Version 4.00\n
              The software can select system address register SRS00 (when this bit is 0) or SRS23 / SRS22 (when this bit is 1) for the SDMA engine.
RW 0x0
27 CMD23E 
              CMD23E - CMD23 Enable\n
              In result of Card Identification process, Host Driver set this bit to 1 if Card supports CMD23 (SCR[33]==1). \n
RW 0x0
26 ADMA2LM 
              ADMA2LM - ADMA2 Length Mode\n
              This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit.\n
              0 - 16-bit Data Length Mode\n
              1 - 26-bit Data Length Mode
RW 0x0
25 Reserved_13 
Reserved bitfield added by Magillem
 RO 0x0
24 LVSIEXEC 
              LVSIEXEC - LVS Identification Execution\n
              Setting this field to 1, generates one pulse on SDCLK output.\n
              This bit does not change while DAT[2] stays LOW. After detecting DAT[2] is HIGH, this field automatically changes its value to 0 confirming end of the Low Voltage Sequence.
RW 0x0
23 SCS 
              SCS - Sampling Clock Select\n
              The host updates this bit when the tuning procedure is finished. If this bit is set to 1, this means that the tuning procedure is successfully completed.\n
              Otherwise it means that procedure failed and clock tuning logic is disabled.\n
              This bit is valid only after the procedure is finished.Writing 1 will be ignored.\n
              Writing 0 will reset and disable tuning block.
RW 0x0
22 EXTNG 
              EXTNG - Execute Tuning\n
              This register controls tuning procedure.\n
              The procedure starts when the bit is set 1.\n
              The procedure can be aborted when the bit is cleared.\n

              The bit is read 1 while the procedure is in progress, and 0 when the procedure is finished.\n
              SCS = 0, EXTNG = 0 - Reset and disable clock tuning logic\n
              SCS = 0, EXTNG = 1 - Reset and restart tuning process\n
              SCS = 1, EXTNG = 0 - Stop tuning procedure\n
              SCS = 1, EXTNG = 1 - Start retuning (without clock tuning logic reset)
RW 0x0
21:20 DSS 
              DSS - Driver Strength Select\n
              This bit controls the electric parameters of I/O driver via \textit{sdphy_dfi_drvss} output of the SD/eMMC Host Controller core). Up to 4 configurations of I/O driver settings can be implemented:
              [list]
              [*] 00 - Driver Type B (default)
              [*] 01 - Driver Type A
              [*] 10 - Driver Type C
              [*] 11 - Driver Type D
              [/list]
              The bit is ignored when the V18SE is cleared.
RW 0x0
19 V18SE 
              V18SE - 1.8V Signaling Enable\n
              This bit controls I/O signaling voltage level.\n
              If the bit is 0 or 1, the I/O uses the 3.3V or 1.8V signaling, respectively.\n
              The SW driver will set this bit 1 when UHS-I mode.\n
              Depend on the selected SD interface mode, the software will set this field as follows:\n
              - 0 - for Default Speed, High Speed mode\n
              - 1 - for UHS-I mode
RW 0x0
18:16 UMS 
              UMS - UHS Mode Select\n
              Used to select one of UHS-I modes.\n
              000b - SDR12\n
              001b - SDR25\n
              010b - SDR50\n
              011b - SDR104\n
              100b - DDR50\n
              101b - Reserved\n
              110b - Reserved\n
              111b - Reserved\n

              The selected UHS-I mode (when value is in range 000b-100b) will be ignored when V18SE is 0.
RW 0x0
15:8 Reserved_7 
Reserved bitfield added by Magillem
 RO 0x0
7 CNIACE 
              CNIACE - Command Not Issued By Auto CMD12 Error\n
              When read as 1, the command was not executed by the Host due to the previous Auto CMD12 error.\n
              When Host detects any error during Auto-CMD12, then all further command generation attempts are blocked. The software reset sequence is needed for recovery.\n
              Bit is set to 0, when Auto CMD23 Error is detected (any of bits SRS15[4:1] is set).
RO 0x0
6 Reserved_6 
Reserved bitfield added by Magillem
 RO 0x0
5 ACRE 
              ACRE - Auto CMD Response Error\n
              When read as 1, means an error is detected in response to Auto Command.
RO 0x0
4 ACIE 
              ACIE - Auto CMD Index Error\n
              When read as 1, means that Command Index error occurred in the Auto CMD response.
RO 0x0
3 ACEBE 
              ACEBE - Auto CMD End Bit Error\n
              When read as 1, indicates that the end bit of the Auto-CMD response is 0.
RO 0x0
2 ACCE 
              ACCE - Auto CMD CRC Error\n
              When read as 1, indicates a CRC error was detected in the Auto CMD response or conflict on the CMD lines is detected:\n
              ACCE(SRS15.2) = 0, ACTE(SRS15.1) = 0 - No error\n
              ACCE(SRS15.2) = 0, ACTE(SRS15.1) = 1 - Auto CMD Timeout error detected\n
              ACCE(SRS15.2) = 1, ACTE(SRS15.1) = 0 - Auto CMD CRC error detected\n
              ACCE(SRS15.2) = 1, ACTE(SRS15.1) = 1 - Conflict on the CMD line detected
RO 0x0
1 ACTE 
              ACTE - Auto CMD Timeout Error\n
              When read as 1, indicates that there was no response within 64 SDCLK clock cycles from the end bit of the Auto CMD or conflict on the CMD lines is detected (see table in SRS15.ACCE field description).\n
              If this bit is set to 1, the other error status bits (SRS15[4:2]) are meaningless.
RO 0x0
0 ACNE 
              ACNE - Auto CMD12 Not Executed\n
              When set to 1, means the host cannot issue Auto CMD12 due to some error. If this bit is set to 1, other error status bits (SRS15[4:1]) are meaningless.\n
              Bit is updated with 0, when Auto CMD23 Error is detected (any of bits SRS15[4:1] is set).
RO 0x0