SRS27 

         
            SRS27 - Preset Value (SDR104 and DDR50)\n
            SRS27[15:0] - SDR104 if:\n
            SRS15.V18SE=1\n
            SRS15.UMS=011b\n

            SRS27[31:16] - DDR50 if:\n
            SRS15.V18SE=1\n
            SRS15.UMS=100b\n

            HWINIT Register - Note this register is hardware initialized after reset and the value read back will match the IP configuration.
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x1080826C

Size: 32

Offset: 0x6C

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SRS27_DSSPV_31_30

RO 0x0

Reserved_3

RO 0x0

SRS27_SDCFSPV_25_16

RO 0x2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SRS27_DSSPV_15_14

RO 0x0

Reserved_1

RO 0x0

SRS27_SDCFSPV_09_00

RO 0x0

SRS27 Fields

Bit Name Description Access Reset
31:30 SRS27_DSSPV_31_30 
              DSSPV## - Driver Strength Select - Preset Value\n
              This field can be used by the software to update SRS15.DSS.
RO 0x0
29:26 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
25:16 SRS27_SDCFSPV_25_16 
              SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n
              This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.
RO 0x2
15:14 SRS27_DSSPV_15_14 
              DSSPV## - Driver Strength Select - Preset Value\n
              This field can be used by the software to update SRS15.DSS.
RO 0x0
13:10 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
9:0 SRS27_SDCFSPV_09_00 
              SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n
              This field can be used by the software to update SRS11.SDCFSH and SRS11.SDCFSL.
RO 0x0