SRS11 

         SRS11 - Host Control 2 (Clock, Timeout, Reset)
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x1080822C

Size: 32

Offset: 0x2C

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_9

RO 0x0

SRDAT

RW 0x0

SRCMD

RW 0x0

SRFA

RW 0x0

Reserved_6

RO 0x0

DTCV

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDCFSL

RW 0x0

SDCFSH

RW 0x0

Reserved_3

RO 0x0

SDCE

RW 0x0

ICS

RO 0x0

ICE

RW 0x0

SRS11 Fields

Bit Name Description Access Reset
31:27 Reserved_9 
Reserved bitfield added by Magillem
 RO 0x0
26 SRDAT 
              SRDAT - Software Reset For DAT Line\n
              When set to 1, resets the logic related to the data path, including data buffers and the DMA logic.\n
              The following registers and bits are cleared:\n
              SRS08 register:
              [list]
              [*] Buffer
              [/list]

              SRS09 register:
              [list]
              [*] Buffer Read Enable
              [*] Buffer Write Enable
              [*] Read Transfer Active
              [*] Write Transfer Active
              [*] DAT Line Active
              [*] Command Inhibit
              [/list]

              DATSRS10 register:
              [list]
              [*] Continue Request
              [*] Stop At Block Gap Request
              [/list]

              SRS12 register:
              [list]
              [*] Buffer Read Ready
              [*] Buffer Write Ready
              [*] DMA Interrupt
              [*] Block Gap Event
              [*] Transfer Complete
              [/list]

              After completing the reset operation, SRS11.SRDAT bit is automatically cleared.
              It takes some time to complete the reset operation, so the software will wait until SRS11.SRDAT=0, and continue the other operations only when SRS11.SRDAT=0.
RW 0x0
25 SRCMD 
              SRCMD - Software Reset For CMD Line\n
              When set to 1, resets the logic related to the command generation and response checking.\n
              The following registers and bits are cleared:
              [list]
              [*] SRS09 register: Command Inhibit CMD
              [*] SRS12 register: Command Complete
              [/list]

              After completing the reset operation, SRS11.SRCMD bit is automatically cleared.
              It takes some time to complete the reset operation, so the software will wait until SRCMD=0, and continue the other operations only when SRS11.SRCMD=0.
RW 0x0
24 SRFA 
              SRFA - Software Reset For All\n
              When set to 1, the entire slot is reset.After completing the reset operation, SRFA bit is automatically cleared. It takes some time to complete the reset operation, so the software will wait until SRFA=0, and continue the other operations only when SRFA=0.\n
              Additionally, after SRFA, software should reset and reinitialize card inserted to the slot.\n
              SD Card Power may be enabled 1 ms after this bit is cleared to ensure SD Card has been reset properly.
RW 0x0
23:20 Reserved_6 
Reserved bitfield added by Magillem
 RO 0x0
19:16 DTCV 
              DTCV - Data Timeout Counter Value\n
              This value determines the interval by which DAT line timeouts are detected.\n
              The interval can be computed as below:
              [list]
              [*] 1111b - Reserved
              [*] 1110b - t_sdmclk*2^(27+2)
              [*] 1101b - t_sdmclk*2^(26+2)
              [*] ...
              [*] 0001b - t_sdmclk*2^(14+2)
              [*] 0000b - t_sdmclk*2^(13+2)
              [/list]
              Where t_sdmclk is the sdmclk clock periodRefer to the Data Timeout Error (SRS12.EDT) register for information on factors which generate data timeouts.
RW 0x0
15:8 SDCFSL 
              SDCFSL - SDCLK Frequency Select (lower part)\n
              This register and SRS11.SDCFSH are used to calculate frequency of SDCLK clock.\n
              The SDCLK frequency is calculated with following expressions:\n
              - sdclk = sdmclk; when (N=0)\n
              - sdclk = sdmclk/2N; when (N>0)\n
              Variable N is concatenation of SRS11.SDCFSH and SRS11.SDCFSL.\n
              The value of SDCFSL, SDCFSH registers can be changed only when SRS11.SDCE (SD Clock Enable)=0.
RW 0x0
7:6 SDCFSH 
SDCFSH - SDCLK Frequency Select (higher part)\n
            This register is an extension to SDCFSL.
 RW 0x0
5:3 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
2 SDCE 
              SDCE - SD Clock Enable\n
              When set to 1, SDCLK clock is enabled.\n
              When cleared to 0, SDCLK clock is stopped.\n
              The host clears SDCE automatically when card is removed from the slot (i.e. after the high to low transition on \textit{pad_mem_ctrl_0} pad).\n
              The SDCLK clock should be stopped by the software when changing the clock divider (i.e. SDCE bit will be cleared before writing SRS11.SDCFSL, SRS11.SDCFSH).
RW 0x0
1 ICS 
              ICS - Internal Clock Stable\n
              When read as 1, indicates that the clock on sdmclk pin of the host is stable after setting ICE to 1.\n
              When read as 0, indicates that the clock is not stable yet (for example the external PLL that generates the clock is not yet locked).\n
              The value of ICS is equal to the actual signal level on ics pin of the host. The user will connect ics to the external PLL if required.
              Otherwise, ics should be connected directly to the ice output of the host.
RO 0x0
0 ICE 
              ICE - Internal Clock Enable\n
              This field is designated to controls (enable/disable) external clock generator (e.g. PLL).
              The ICE bits of every slot are logically OR-ed together and then drive the ice pin.
              It means, the ice pin is 0 only when ICE in 0 for every slot implemented inside the host.\n
              The ice pin is 1 if at least one of the ICE bits is set to 1.\n
              When set to 0, the clock on sdmclk pin can be stopped externally.\n
              If the sdmclk is stopped, then host goes to a very low power state.
              The hosts registers are still operable (read and written operation are valid) even if the clock on sdmclk is stopped.\n
              Setting of the ICE bit does not affect card detection. It means, the card detection works even if the clock on sdmclk is stopped.
RW 0x0