SRS14

         SRS14 - Error/Normal Signal Enable


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`	`0x10808200`	`0x10808238`

Size: 32

Offset: 0x38

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_22` `RO 0x0`				`ERSP_IE` `RW 0x0`	`Reserved_21` `RO 0x0`	`EADMA_IE` `RW 0x0`	`EAC_IE` `RW 0x0`	`ECL_IE` `RW 0x0`	`EDEB_IE` `RW 0x0`	`EDCRC_IE` `RW 0x0`	`EDT_IE` `RW 0x0`	`ECI_IE` `RW 0x0`	`ECEB_IE` `RW 0x0`	`ECCRC_IE` `RW 0x0`	`ECT_IE` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_11` `RO 0x0`	`CQINT_IE` `RW 0x0`	`FXE_IE` `RW 0x0`	`Reserved_9` `RO 0x0`				`CINT_IE` `RW 0x0`	`CR_IE` `RW 0x0`	`CIN_IE` `RW 0x0`	`BRR_IE` `RW 0x0`	`BWR_IE` `RW 0x0`	`DMAINT_IE` `RW 0x0`	`BGE_IE` `RW 0x0`	`TC_IE` `RW 0x0`	`CC_IE` `RW 0x0`

SRS14 Fields


Bit	Name	Description	Access	Reset
31:28	`Reserved_22`	Reserved bitfield added by Magillem	`RO`	`0x0`
27	`ERSP_IE`	ERSP_IE - Response Error Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
26	`Reserved_21`	Reserved bitfield added by Magillem	`RO`	`0x0`
25	`EADMA_IE`	EADMA_IE - ADMA Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
24	`EAC_IE`	EAC_IE - Auto CMD Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
23	`ECL_IE`	ECL_IE - Current Limit Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
22	`EDEB_IE`	EDEB_IE - Data End Bit Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
21	`EDCRC_IE`	EDCRC_IE - Data CRC Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
20	`EDT_IE`	EDT_IE - ata Timeout Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
19	`ECI_IE`	ECI_IE - Command Index Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
18	`ECEB_IE`	ECEB_IE - Command End Bit Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
17	`ECCRC_IE`	ECCRC_IE - Command CRC Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
16	`ECT_IE`	ECT_IE - Command Timeout Error Interrupt Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
15	`Reserved_11`	Reserved bitfield added by Magillem	`RO`	`0x0`
14	`CQINT_IE`	CQINT_IE - Command Queuing - Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
13	`FXE_IE`	FXE_IE - FX Event Interrupt Enable \n 1 - enabled\n 0 - masked	`RW`	`0x0`
12:9	`Reserved_9`	Reserved bitfield added by Magillem	`RO`	`0x0`
8	`CINT_IE`	CINT_IE - Card Interrupt - Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
7	`CR_IE`	CR_IE - Card Removal Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
6	`CIN_IE`	CIN_IE - Card Insertion Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
5	`BRR_IE`	BRR_IE - Buffer Read Ready Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
4	`BWR_IE`	BWR_IE - Buffer Write Ready Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
3	`DMAINT_IE`	DMAINT_IE - DMA Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
2	`BGE_IE`	BGE_IE - Block Gap Event Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
1	`TC_IE`	TC_IE - Transfer Complete Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
0	`CC_IE`	CC_IE - Command Complete Interrupt Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`