SRS16 

         
            SRS16 - Capabilities #1
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x10808240

Size: 32

Offset: 0x40

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SLT

RO 0x0

AIS

RO 0x0

A64SV3

RO 0x1

A64SV4

RO 0x1

VS18

RO 0x1

VS30

RO 0x1

VS33

RO 0x1

SRS

RO 0x0

DMAS

RO 0x1

HSS

RO 0x1

ADMA1S

RO 0x0

ADMA2S

RO 0x1

EDS8

RO 0x0

MBL

RO 0x2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BCSDCLK

RO 0xC8

TCU

RO 0x1

Reserved_1

RO 0x0

TCF

RO 0x32

SRS16 Fields

Bit Name Description Access Reset
31:30 SLT 
              SLT - Slot Type\n
              These bits inform what type of slot is provided.\n
              [list]
              [*] 00 - Removable Card Slot
              [*] 01 - Embedded Slot for One Device
              [*] 10 - Shared Bus Slot
              [*] 11 - Reserved
              [/list]
RO 0x0
29 AIS 
              AIS - Asynchronous Interrupt Support\n
              0 - not supported\n
RO 0x0
28 A64SV3 
              A64SV3 - 64-bit System Addressing Support\n
              0 - 64-bit Addressing for V3 is not supported\n
              1 - 64-bit Addressing for V3 is supported
RO 0x1
27 A64SV4 
              A64SV4 - 64-bit System Addressing Support for V4\n
              0 - 64-bit Addressing for V4 is not supported\n
              1 - 64-bit Addressing for V4 is supported
RO 0x1
26 VS18 
              VS18 - Voltage Support 1.8V\n
              0 - not supported\n
              1 - supported
RO 0x1
25 VS30 
              VS30 - Voltage Support 3.0V\n
              0 - not supported\n
              1 - supported
RO 0x1
24 VS33 
              VS33 - Voltage Support 3.3V\n
              0 - not supported\n
              1 - supported
RO 0x1
23 SRS 
              SRS - Suspend / Resume Support\n
              0 - not supported\n
              1 - supported\n
              The host controller does not support Suspend / Resume mechanism.
RO 0x0
22 DMAS 
              DMAS - SDMA Support\n
              0 - not supported\n
              1 - supported\n
              This bit defines whether the SDMA is supported.
RO 0x1
21 HSS 
              HSS - High Speed Support\n
              0 - not supported\n
              1 - supported
 RO 0x1
20 ADMA1S 
              ADMA1S - ADMA1 Support\n
              0 - not supported\n
              1 - supported
RO 0x0
19 ADMA2S 
              ADMA2S - ADMA2 Support\n
              0 - not supported\n
              1 - supported
RO 0x1
18 EDS8 
              8EDS - 8-bit Embedded Device Support\n
              0 - not supported\n
              1 - supported\n
              If this bit is 0, the SRS10.EDTW register is not implemented.
RO 0x0
17:16 MBL 
              SRS16.MBL - Max Block Length\n
              This value indicates the maximum block size that can be transferred by the host. Three sizes can be defined as indicated below:
              [list]
              [*] 00b - 512 Bytes
              [*] 01b - 1024 Bytes
              [*] 10b - 2048 Bytes
              [*] 11b - Reserved
              [/list]
              The physical FIFO buffer size is defined by the separate FIFODEPTH generic parameter, and the physical buffer size is equal to 2^FIFODEPTH * 8 bytes.
              Therefore, the Maximum Block Size defined by MBL will always be less or equal to the physical buffer size.
RO 0x2
15:8 BCSDCLK 
              BCSDCLK - Base Clock Frequency for SD Clock\n
              Field defines the base clock frequency for the SD Clock in 1MHz units.
              The base clock is the clock sourced to sdmclk pin of the host. The maximum clock frequency supported is between 10MHz to 255MHz.\n
              If BCSDCLK = 0, the Host System has to obtain the clock information via another method (i.e. not defined by the specification).
RO 0xC8
7 TCU 
              TCU - Timeout Clock Unit\n
              Field defines the frequency unit for the SRS16.TCF.\n
              0 - kHz\n
              1 - MHz
RO 0x1
6 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
5:0 TCF 
              TCF - Timeout Clock Frequency\n
              Defines the base clock frequency used to detect Data Timeout Error.
              The SRS16.TCU bit determines the unit used.\n
              111111b - 63kHz(SRS16.TCU=0) or 63MHz(SRS16.TCU=1)\n
              111110b - 63kHz(SRS16.TCU=0) or 63MHz(SRS16.TCU=1)\n
              ...\n
              000001b - 1kHz(SRS16.TCU=0) or 1MHz(SRS16.TCU=1)\n
              000000b - Host System has to obtain the clock information via another method (i.e. not defined by the spec).
RO 0x32