SRS08

         SRS08 - Data Buffer


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`	`0x10808200`	`0x10808220`

Size: 32

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`BDP` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`BDP` `RW 0x0`

SRS08 Fields

Bit Name Description Access Reset

31:0

Bit	Name	Description	Access	Reset
31:0	`BDP`	BDP - Buffer Data Port\n The field is to access the internal buffer (data block) in non-DMA transfer mode. 8-bit, 16-bit, or 32-bit access to SRS08 is possible with the following restrictions:\n - Only sequential contiguous access in Little Endian mode is possible. For example, if the software accesses BDP[7:0], then the next transfer will access BDP[15:8]. No byte skipping is allowed.\n - Each new block will start at the least significant byte of BDP, which is BDP[7:0].\n - If the block size is not a multiple of 32-bits, and the software accesses BDP using 32-bit words, then the excess bytes of the last word are ignored. This allows the software driver to use only 32-bit data transfers regardless of the block size.\n - Access to the register with precaution - the FIFO pointers can be damaged when buffer is not ready or when number of accesses exceed the transfer block size (SRS01.TBS).\n Following shows all transfers (byte enable variations) that are allowed on SRS08:\n Transfer width = 32-bit: [list] [] be[3:0] = 'b1111 -> BDP[31:0] [/list] Transfer width = 16-bit:\n [list] [] be[3:0] = 'b0011 -> BDP[15:0] [] be[3:0] = 'b1100 -> BDP[31:16] [/list] Transfer width = 8-bit:\n [list] [] be[3:0] = 'b0001 -> BDP[7:0] [] be[3:0] = 'b0010 -> BDP[15:8] [] be[3:0] = 'b0100 -> BDP[23:16] [*] be[3:0] = 'b1000 -> BDP[31:24] [/list]	`RW`	`0x0`

BDP

              BDP - Buffer Data Port\n
              The field is to access the internal buffer (data block) in non-DMA transfer mode.
              8-bit, 16-bit, or 32-bit access to SRS08 is possible with the following restrictions:\n
              - Only sequential contiguous access in Little Endian mode is possible.
              For example, if the software accesses BDP[7:0], then the next transfer will access BDP[15:8]. No byte skipping is allowed.\n
              - Each new block will start at the least significant byte of BDP, which is BDP[7:0].\n
              - If the block size is not a multiple of 32-bits, and the software accesses BDP using 32-bit words, then the excess bytes of the last word are ignored.
              This allows the software driver to use only 32-bit data transfers regardless of the block size.\n
              - Access to the register with precaution - the FIFO pointers can be damaged when buffer is not ready or when number of accesses exceed the transfer block size (SRS01.TBS).\n

              Following shows all transfers (byte enable variations) that are allowed on SRS08:\n
              Transfer width = 32-bit:
              [list]
              [*] be[3:0] = 'b1111 -> BDP[31:0]
              [/list]

              Transfer width = 16-bit:\n
              [list]
              [*] be[3:0] = 'b0011 -> BDP[15:0]
              [*] be[3:0] = 'b1100 -> BDP[31:16]
              [/list]

              Transfer width = 8-bit:\n
              [list]
              [*] be[3:0] = 'b0001 -> BDP[7:0]
              [*] be[3:0] = 'b0010 -> BDP[15:8]
              [*] be[3:0] = 'b0100 -> BDP[23:16]
              [*] be[3:0] = 'b1000 -> BDP[31:24]
              [/list]

RW

0x0