SRS00 

         SRS00 - SDMA System Address / Argument 2
 / 32-bit block count\n
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x10808200

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SAAR

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SAAR

RW 0x0

SRS00 Fields

Bit Name Description Access Reset
31:0 SAAR 
              SAAR - System Address / Argument 2
              / 32-bit block count\n
              This field is used as:
              [list]
              [*] 32-bit Block Count register
              [*] SDMA system memory address [*] Auto CMD23 Argument [/list]

              \n
              32-bit block count:\n
              This field enables to define number of data blocks for the next transfer.\n
              It is used when Host Controller is set in version 4 compatibility mode (SRS15.HV4E=1), Block Count Enable is enabled (SRS03.BCE=1) and 16-bit Block Count for Current Transfer is cleared (SRS01.BCCT=0).\n
              Value of this field is decremented after each block transfer. When this field is set 0, no data blocks is transferred.\n
              Software should not read this field during data transfer as return unexpected value. Write to this field during data transfer are ignored.\n
              When Host Controller is not set in version 4 compatibility mode (SRS15.HV4E=0) or 16-bit Block Count for Current Transfer is not equal to 0, (SRS01.BCCT) defines the block count.\n
              [list] [*] 00000000h - no block transfer [*] 00000001h..FFFFFFFFh - 1..4294967295 block(s) transfer. [/list]

              \n
              System Address:\n
              This register is used as base address when SDMA engine is selected (SRS03.DMAE=1 and SRS10.DMASEL=0) and SRS15.HV4E=0.\n
              When SDMA stops at SDMA Buffer Boundary, software updates System Address and write to SAAR[31:24] resumes SDMA transfer. Software driver sets address to the next data location in system memory.

              \n
              Auto CMD23 Argument:\n
              Auto CMD23 can be used in non-DMA or ADMA2 mode (when SRS15.HV4E=0) or in non-DMA, SDMA, ADMA2 mode (when SRS15.HV4E=1).
RW 0x0