SRS13

         SRS13 - Error/Normal Status Enable


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`	`0x10808200`	`0x10808234`

Size: 32

Offset: 0x34

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_22` `RO 0x0`				`ERSP_SE` `RW 0x0`	`Reserved_21` `RO 0x0`	`EADMA_SE` `RW 0x0`	`EAC_SE` `RW 0x0`	`ECL_SE` `RW 0x0`	`EDEB_SE` `RW 0x0`	`EDCRC_SE` `RW 0x0`	`EDT_SE` `RW 0x0`	`ECI_SE` `RW 0x0`	`ECEB_SE` `RW 0x0`	`ECCRC_SE` `RW 0x0`	`ECT_SE` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_11` `RO 0x0`	`CQINT_SE` `RW 0x0`	`FXE_SE` `RW 0x0`	`Reserved_9` `RO 0x0`				`CINT_SE` `RW 0x0`	`CR_SE` `RW 0x0`	`CIN_SE` `RW 0x0`	`BRR_SE` `RW 0x0`	`BWR_SE` `RW 0x0`	`DMAINT_SE` `RW 0x0`	`BGE_SE` `RW 0x0`	`TC_SE` `RW 0x0`	`CC_SE` `RW 0x0`

SRS13 Fields


Bit	Name	Description	Access	Reset
31:28	`Reserved_22`	Reserved bitfield added by Magillem	`RO`	`0x0`
27	`ERSP_SE`	ERSP_SE - Response Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
26	`Reserved_21`	Reserved bitfield added by Magillem	`RO`	`0x0`
25	`EADMA_SE`	EADMA_SE - ADMA Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
24	`EAC_SE`	EAC_SE - Auto CMD Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
23	`ECL_SE`	ECL_SE - Current Limit Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
22	`EDEB_SE`	EDEB_SE - Data End Bit Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
21	`EDCRC_SE`	EDCRC_SE - Data CRC Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
20	`EDT_SE`	EDT_SE - Data Timeout Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
19	`ECI_SE`	ECI_SE - Command Index Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
18	`ECEB_SE`	ECEB_SE - Command End Bit Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
17	`ECCRC_SE`	ECCRC_SE - Command CRC Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
16	`ECT_SE`	ECT_SE - Command Timeout Error Status Enable (SD mode only)\n 1 - enabled\n 0 - masked	`RW`	`0x0`
15	`Reserved_11`	Reserved bitfield added by Magillem	`RO`	`0x0`
14	`CQINT_SE`	CQINT_SE - Command Queuing Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
13	`FXE_SE`	FXE_SE - FX Event Status Enable \n 1 - enabled\n 0 - masked	`RW`	`0x0`
12:9	`Reserved_9`	Reserved bitfield added by Magillem	`RO`	`0x0`
8	`CINT_SE`	CINT_SE - Card Interrupt Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
7	`CR_SE`	CR_SE - Card Removal Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
6	`CIN_SE`	CIN_SE -Card Insertion Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
5	`BRR_SE`	BRR_SE - Buffer Read Ready Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
4	`BWR_SE`	BWR_SE - Buffer Write Ready Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
3	`DMAINT_SE`	DMAINT_SE - DMA Interrupt Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
2	`BGE_SE`	BGE_SE - Block Gap Event Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
1	`TC_SE`	TC_SE - Transfer Complete Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`
0	`CC_SE`	CC_SE - Command Complete Status Enable\n 1 - enabled\n 0 - masked	`RW`	`0x0`