SRS09

Reserved bitfield added by Magillem

              SCMDS - Sub Command Status\n
              The SRS03 register and Response registers (SRS04-SRS07) are commonly used
              for main command and sub command. This status is used to distinguish
              which response error statuses, main command or sub command, indicated the
              Error Interrupt Status register.
              Just before reading of this register, the SRS03.SCF is copied to this status.
              This status is effective when not only Response Error interrupt is generated
              (SRS12.ERSP) but also data error interrupt is generated with
              Command Not Issued by Error (SRS09.CNIBE) or Auto CMD Error (SRS12.EAC)
              interrupt is generated with Command Not Issued by Error by Auto CMD12 (SRS15.CNIACE). \n
              SRS09.SCMDS indicate which command is not issued (main or sub).\n
            

              CNIBE - Command Not Issued By Error\n
              Setting of CNIBE status indicates that a command cannot be issued to an error,
              except Auto CMD12 error. (Equivalent error status by Auto CMD12 error is defined as SRS15.CNIACE.)
              This status is set to 1 when Host Controller cannot issue a command after setting Command register.\n
            

              LVSIRSLT - LVS Identification Result\n

              Result of the Low Voltage Signaling Identification. This bit contains a valid information only when LVS Identification Execution bit has changed from 1 to 0.

              This field is cleared when any of following condition is met:
              (a) SD Bus Power for VDD1 is set to 0
              (b) Card Inserted indicates card removal
              (c) HRS00.SWR (software reset)

            

Reserved bitfield added by Magillem

              CMDSL - CMD Line Signal Level\n
              The value is equal to the actual signal level on CMD line of the SD interface (pad_mem_cmd).\n
              Is useful for debugging purposes.
            

              DATSL1 - DAT[3:0] Line Signal Level\n
              The value is equal to the actual signal level on DAT input pad of the SD/eMMC interface:\n
              [list]
              [*] SRS09.23 - pad_mem_data[3]
              [*] SRS09.22 - pad_mem_data[2]
              [*] SRS09.21 - pad_mem_data[1]
              [*] SRS09.20 - pad_mem_data[0]
              [/list]
            

              WPSL - Write Protect Switch Pin Level\n
              The value is equal to the actual signal level on Write Protect pad of the SD/eMMC interface (\textit{pad_mem_wpbar}).
              [list]
              [*] 1 - means that the write operation is enabled
              [*] 0 - means that the write operations is disabled
              [/list]
            

              CDSL - Card Detect Pin Level\n
              The value is equal to the inverted signal level on Card Detect pin of the SD/eMMC interface (\textit{pad_mem_ctrl_0}).
              [list]
              [*] 1 - means that the card is inserted
              [*] 0 - means no card is inside the slot
              [/list]
              Debouncing is not performed on CDSL, therefore the use of Card Inserted (CI) bit is recommended during normal work.\n
              CDSL bit is useful only for debugging purposes.
            

              CSS - Card State Stable\n
              Indicates if Card Detect Pin Level (CDSL) is stable.
              [list]
              [*] 1 - means that the CDSL value is stable
              [*] 0 - means that the CDSL is not stable (during card insertion/removal or during the reset)
              [/list]
              Field is useful for debugging purposes.
            

              CI - Card Inserted\n
              Indicates if the card is inserted inside the slot.
              [list]
              [*] 0 - no card in slot
              [*] 1 - card is inserted
              [/list]
              Unlike SRS09.CDSL, value of SRS09.CI bit is guaranteed to be stable (i.e. debouncing is performed on this bit).
              Use of this bit is recommended during the normal operation of host.
            

Reserved bitfield added by Magillem

              BRE - Buffer Read Enable\n
              This field represents data buffer (SRS08.BDP) state for read transfer in non-DMA mode.\n
              [list]
              [*] 1 - valid data can be read from the data buffer
              [*] 0 - no valid data inside the data buffer
              [/list]
              After reading the entire data block, this bit changes to 0.
            

              BWE - Buffer Write Enable\n
              This bit represents data buffer (SRS08.BDP) state for write transfer in non-DMA mode.\n
              [list]
              [*] 1 - data can be written to the data buffer
              [*] 0 - data cannot be written
              [/list]
              After reading the entire data block, this changes to 0.\n
              This bit will be cleared in case of SBGR at non-DMA write transfer (even if the internal buffer is ready). The buffer must not be written after the SBGR.
              If the BWR was set, the only action from the S/W is to clear the interrupt status.
            

              RTA - Read Transfer Active\n
              Indicates the status of the read data transfer.
              [list]
              [*] 0 - no data read transfer in progress
              [*] 1 - data read transfer in progress
              [/list]
              Bit is set 1 after sending the read command, or after restarting the read transfer by the Continue Request (SRS10.CREQ).\n
              Bit is set 0 by the hardware after the last block of the read transfer, or after stopping the read transfer by the Stop at Block Gap Request (SRS10.SBGR).\n
              In both cases, the entire data is to be read by the system from the internal data buffer before setting this bit to 0.
              In other words, SRS09.RTA=0 means that the entire data is already transferred to the system, and internal data buffer is empty.
            

              WTA - Write Transfer Active\n
              Indicates the status of the write data transfer.
              [list]
              [*] 0 - no data write transfer in progress
              [*] 1 - data write transfer in progress
              [/list]
              Bit is set 1 after sending the write command, or after restarting the write transfer by the Continue Request (SRS10.CREQ).\n
              Bit is set 0 by the hardware after the last block of the write transfer, or after stopping the write transfer by the Stop at Block Gap Request (SRS10.SBGR).\n
              In both cases, the entire data has to be transferred to the card from the internal data buffer before setting this bit to 0.
              In other words, WTA=0 means that the entire data is already transferred to the card, and CRC response for the last data block is already received.
            

              DATSL2 - DAT[7:4] Line Signal Level\n
              The value is equal to the actual signal level on DAT input pad of the SD/eMMC interface:\n
              [list]
              [*] SRS9.7 - pad_mem_data[7]
              [*] SRS9.6 - pad_mem_data[6]
              [*] SRS9.5 - pad_mem_data[5]
              [*] SRS9.4 - pad_mem_data[4]
              [/list]
            

Reserved bitfield added by Magillem

              DLA - DAT Line Active\n
              Indicates if the DAT lines of SD interface are currently in use.
              [list]
              [*] 1 - DAT lines are active (in use)
              [*] 0 - DAT lines are released (not in use)
              [/list]
              This bit set to 1, when Read or Write Transfer bits are active (SRS09.RTA=1 or SRS09.WTA=1), or if the card indicates busy state on the DAT lines.
              The card can become busy immediately after the write operation, or after command which requires response with busy.\n
              Falling edge of this bit (change from 1 to 0) directly triggers Transfer Complete Interrupt (SRS12.TC).
            

              CIDAT - Command Inhibit DAT\n
              Indicates if the host can issue a command which uses DAT line. Commands which use DAT line include write and read data commands and commands with busy response.
              [list]
              [*] 1 - command using DAT line cannot be sent
              [*] 0 - command using DAT line can be sent
              [/list]
              When CIDAT=1 then the SRS03[15:0] is write-protected. The software can write SRS03[15:0] only when CIDAT=0.
            

              CICMD - Command Inhibit CMD\n
              Indicates if the host can issue a command.
              [list]
              [*] 0 - command can be sent
              [*] 1 - command cannot be sent
              [/list]
              If this bit is 0, indicates the CMD line is not in use and the Host Controller can issue an SD command using the CMD line.\n
              This bit is set immediately after the CI is written, indicating start of command transmission.\n
              This bit is cleared when the command response is received.\n
              Even if the Command Inhibit DAT is set to 1, commands using only the CMD line can be issued if the Command Inhibit CMD is 0.\n
              Change from 1 to 0 directly triggers Command Complete Interrupt (SRS12.CC).